Hewlett-Packard Development Company, L.p.

John A Benavides

Tyler J Johnson

Ryan Lee Akkerman

Richard W Adkisson

Dean T Lindsay

Kenneth D Holloway

One disclosed embodiment may comprise a system that includes a qualification system that qualifies data on an associated bus for capture and provides a qualification signal as a function of at least one signal that describes a characteristic of the data on the associated bus. A data capture system stores qualified data from the associated bus based on the qualification signal and a trigger signal, the trigger signal defining a capture session.

System and method to qualify data capture

A system includes a monitoring system that provides at least one signal as a function of at least some data provided on a bus. A measure of performance for the at least some data is adjusted based on the at least one signal. An analysis system is operative to perform logic analysis of the data on the bus as a function of the at least one signal.

System and method for data analysis

One disclosed embodiment may comprise an application specific integrated circuit (ASIC). The ASIC includes memory that stores condition data defining conditions for enabling transitions among a plurality of states and next state data defining a next state associated with each of the respective conditions. A state machine circuit employs the condition data and the next state data to transition from a current state of the state machine circuit to a next state as a function of applying at least one condition relative to input data. The at least one condition is defined by condition data that is associated with the current state. The state machine circuit associates next state data with the at least one condition based on the current state of the state machine circuit. A control circuit provides a trigger signal in response to the current state of the state machine circuit transitioning to at least one predefined state of the plurality of states.

System and method for generating a trigger signal

One disclosed embodiment may comprise a system that includes a data capture system that stores a set of data from an associated data source in response to a store signal while enabled based on a control signal. A control system provides the control signal based on a number of store cycles relative to an event to define the set of data, the number of store cycles varying based on the store signal.

System and method to control data capture

An embodiment of this invention provides a system and method for indicating the orientation of a packaged IC in a socket. An LED is physically mounted to a socket. One lead of the LED is electrically connected to a positive voltage through a socket hole on the socket. When the orientation of the IC package in the socket is correct, the other lead of the LED is connected to a ground path on the packaged IC. As a result, the LED is activated indicating the orientation of the packaged IC is correct.

Method and system for sensing IC package orientation in sockets

An embodiment of this invention provides a system and method for sensing the status of a ZIF socket lever. An LED is physically mounted to a socket. One lead of the LED is electrically connected to a positive voltage through a electrical contact on the socket. When the ZIF socket lever is closed, the other lead of the LED is connected to a ground. As a result, the LED is activated indicating the ZIF socket lever is closed.

Method and system for sensing the status of a ZIF socket lever

A system and method for testing at least one interface of a digital integrated circuit while at least one other interface of the digital integrated circuit operates in a normal mode is disclosed. Each interface includes at least one boundary scan cell such that each boundary scan cell is electrically coupled to a pin of the digital integrated circuit. The method includes selectively categorizing at least one interface into a first category. At least one other interface is selectively categorized into a second category. A first mode signal is provided to the interfaces categorized into the test mode category such that the interfaces categorized into the test mode category operate in a test mode. A second mode signal is provided to the interfaces categorized into the normal operation mode category such that the interfaces categorized into the normal operation mode category operate in a normal operation mode.

System and method for testing an interface between two digital integrated circuits

The present invention is generally related to a system and method for conducting parallel testing of IEEE1149.1 compliant integrated circuits hardware via comparing results generated by integrated circuits under evaluation in accordance with IEEE1149.1 JTAG/IEEE standard test access port and boundary scan architecture provisions, with a master reference signal to determine whether the integrated circuit is functioning properly. There is provided a multi-input scan chain select unit for receiving a selected group of integrated circuit test data inputs. There is provided a comparator unit for comparing each of the selected integrated circuit test data inputs with a predetermined reference signal and determining whether they are the same or not. Malfunctioning integrated circuits are identified based upon results of the comparison.

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Garland, TX, United States of America

John A Benavides