Intel Corporation

John A Bayliss

George W Cox

Kevin C Kahn

Gurdev Dave Singh

Craig B Peterson

Doran K Wilde

Stephen R Colley

William S Richardson

Bert E Forbes

Dorn K Wilde

Robert J Koehler

Roy H Kravitz

An instruction translator unit which receives an instruction stream from a main memory of a microprocessor, for latching data fields, for generating microinstructions necessary to emulate the function encoded in an instruction, and for transferring the data and microinstructions to a microinstruction execution unit over an output bus. The instruction unit includes an instruction decoder (ID) which interprets the fields of received instructions and generates single forced microinstructions and starting addresses of multiple-microinstruction routines. A microinstruction sequencer (MIS) accepts the forced microinstructions and the starting addresses and places on the output bus correct microinstruction sequences necessary to execute the received instruction. The microinstruction routines are stored in a read-only memory (ROM) in the MIS. The starting addresses received from the ID are used to index into and to fetch these microinstructions from the ROM. Forced microinstructions bypass the ROM and are transferred directly by the MIS to the execution unit. The ID processes macroinstructions comprised of variable bit length fields by utilizing an extractor in conjunction with a bit pointer (BIP) for stripping off the bits comprising a particular field. The extracted field is presented to a state machine which decodes the particular field and generates data, microinstructions and starting addresses relating to the particular field for use by the MIS. The state machine then updates the BIP by the bit count of the particular field so that it points to the next field to be extracted.

Macroinstruction translator unit for use in a microprocessor

A microprocessor receives addresses and data from a peripheral subsystem for use in subsequently accessing portions of the main memory of a data processing system in a controlled and protected manner. Each of the addresses is used to interrogate an associative memory to determine if the address falls within one of the subranges for a 'window' on the main memory address space. If the address matches, then it is used to develop a corresponding address on the main memory address space. The data associated with the peripheral subsystem address is then passed through the interface and into the main memory at the translated memory address. Data transfer is improved by buffering blocks of data on the microprocessor. Data bytes are written into the buffer at a slower rate than data blocks are read out of the buffer and into main memory. A buffer bypass register allows single bytes of data to be transferred to a single address by bypassing the buffer. Address development and memory response signals are generated by the microprocessor rather than the peripheral subsystem processor for block transfers.

Microprocessor providing an interface between a peripheral subsystem and

An input/output processor architecture for providing an interface between peripheral subsystems and a generalized data processor. The interface processor enables data to be transferred between two address spaces (the generalized data processor address space and an external processor I/O address space) by mapping a portion of the I/O address space into a portion of the GDP address space. This mapping facility provides the peripheral subsystem with a 'window' into the associated GDP subsystem. It accepts addresses within a certain subrange, or subranges, and translates them into references into one or more GDP data segments. A function-request facility provides a functional capability over certain objects within the GDP address space. The two facilities provide software on an external processor with a window into the address space of the GDP that enables the software, via the function request means, to send messages to and receive messages from the GDP and to manipulate an environment provided for the external processor within its address space.

Input/output data processing system

The data processing capacity of a practical semiconductor computer system, having both local and system buses, can be expanded both in degree of complexity and magnitude by providing a method and means for cooperatively and concurrently coprocessing digital information among a plurality of processors sharing the same local bus and collectively accessing the system bus as a system unit. In other words, a central processor has primary control and access to a local bus and may have access to a system or common bus shared among many other processors. Also sharing the local bus with the central processor is a plurality of specialized or dedicated processors which are continuously apprised of or actively monitor the internal operational status and operation then being performed by the central processor. The active monitoring of the activity of the other processors sharing the local bus distinguishes these dedicated processors from conventional direct memory accessing processors. Certain ones of the instructions fetched simultaneously by the central processor and the specialized processor from the system memory are reserved for execution in one of the dedicated processors which then shares the local bus with the central processor by means of communicating through a plurality of signals with respect to the status, mode, arbitration, and control of the local bus.

Apparatus and method for cooperative and concurrent coprocessing of

A random access memory is combined with a programmable logic array to count time pulses within an integrated circuit watch. A master oscillator drives the internal timing clocks and serves as a time standard for a timing and control circuit means which manipulates data within the random access memory. The timing and control circuit may contain a programmable read-only memory so that words stored within the random access memory may be read, and manipulated, in a selected sequence. The programmable logic array increments the word selectively read from the random access memory, compares it to a limit value and generates one or more flags according to the desired data manipulation. Words stored within the random access memory may be selectively displayed by a liquid crystal display or light emitting diode display in a selected format determined by the programmable read-only memory. A driver circuit coupled to the display may also contain a read-only memory so that the data may be displayed in a selected one of plurality of display fonts. The operational and display modes may be customized by appropriately modifying the programmable logic array and read-only memories without altering the system architecture.

Growing community of inventors

Portland, OR, United States of America

John A Bayliss