Kabushiki Kaisha Toshiba

Kabsuhiki Kaisha Toshiba

Johji Nishio

Chiharu Ota

Tatsuo Shimizu

Takashi Shinohe

Ryosuke Iijima

Hidetoshi Fujimoto

Hiroshi Kono

Kazuhiko Itaya

Takuma Suzuki

Toshihide Ito

Yukio Nakabayashi

Makoto Mizukami

Kazuto Takao

Masayuki Ishikawa

Shinya Nunoue

Mariko Suzuki

Genichi Hatakoshi

Mitsuhiro Kushibe

Lisa Sugiura

Masahiro Yamamoto

Teruyuki Ohashi

Takashi Fujii

Shinji Saito

Hideto Sugawara

Yasuo Ohba

John Rennie

Ako Hatano

Hiroaki Yoshida

Masaaki Onomura

Masayuki Watanabe

Kazutaka Terashima

Shinya Kyogoku

Tetsuo Hatakeyama

Masaru Furukawa

Syoichi Washizuka

Norio Iizuka

Chiharu Nozaki

Hiromoto Fujita

According to one embodiment, a wafer includes a base body including a first surface, and a crystal layer provided on the first surface. The crystal layer includes first stacking faults and one or second stacking faults. One of the first stacking faults includes a first long side, a first short side, and a first hypotenuse. A position of the first long side in a first direction from the base body to the crystal layer is between the base body in the first direction and a first corner portion in the first direction. One of the one or the plurality of second stacking faults includes a second long side, a second short side, and a second hypotenuse. A position of a second corner portion in the first direction is between the base body in the first direction and the second long side in the first direction.

Wafer having a silicon carbide crystal layer with stacking faults provided on a silicon carbide base body and semiconductor device manufactured using the wafer

A semiconductor device according to an embodiment includes: a silicon carbide layer; a silicon oxide layer; and a region disposed between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration equal to or more than 1×10cm. Nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region have a peak in the region, a nitrogen concentration at a position 1 nm away from the peak to the side of the silicon oxide layer is equal to or less than 1×10cm, and a carbon concentration at the position is equal to or less than 1×10cm.

Semiconductor device, method for manufacturing semiconductor device, inverter circuit, drive device, vehicle, and elevator

According to one embodiment, a semiconductor device includes a silicon carbide member. The silicon carbide member includes an operating region including at least one of a diode or a transistor, and a first element region including at least one element selected from the group consisting of Ar, V, Al and B. The first element region includes a first region and a second region. A first direction from the first region toward the second region is along a [1-100] direction of the silicon carbide member. The operating region is between the first region and the second region in the first direction. The first element region does not include a region overlapping the operating region in a second direction along a [11-20] direction of the silicon carbide member. Or the first element region includes a third region overlapping the operating region in the second direction.

Semiconductor device

A semiconductor device according to an embodiment includes: a silicon carbide layer; a silicon oxide layer; and a region disposed between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration equal to or more than 1×10cm. A nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region have a peak in the region, a nitrogen concentration at a first position 1 nm away from the peak to the side of the silicon oxide layer is equal to or less than 1×10cmand a carbon concentration at the first position is equal to or less than 1×10cm, and a nitrogen concentration at a second position 1 nm away from the peak to the side of the silicon carbide layer is equal to or less than 1×10cm.

According to one embodiment, a method for manufacturing a substrate is disclosed. The method can include preparing a structure body. The structure body includes a first semiconductor member and a second semiconductor member. The first semiconductor member includes silicon carbide including a first element. The second semiconductor member includes silicon carbide including a second element. The first element includes at least one selected from a first group consisting of N, P, and As. The second element includes at least one selected from a second group consisting of B, Al, and Ga. The method can include forming a hole that extends through the second semiconductor member and reaches the first semiconductor member. In addition, the method can include forming a third semiconductor member in the hole. The third semiconductor member includes silicon carbide including a third element. The third element includes at least one selected from the first group.

Method for manufacturing substrate, method for manufacturing semiconductor device, substrate, and semiconductor device

A semiconductor device according to an embodiment includes: a silicon carbide layer; a silicon oxide layer; and a region disposed between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration equal to or more than 1&#xd7;10cm. Nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region have a peak in the region, a nitrogen concentration at a position 1 nm away from the peak to the side of the silicon oxide layer is equal to or less than 1&#xd7;10cm, and a carbon concentration at the position is equal to or less than 1&#xd7;10cm.

This semiconductor device according to an embodiment includes: a silicon carbide layer; a gate electrode; a silicon oxide layer between the silicon carbide layer and the gate electrode; and a region between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration not less than 1&#xd7;10cm. A nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region has its peak in the region, and a state density Zin a portion is not more than 1&#xd7;10cm. The portion is within 100 nm from the silicon oxide layer toward the silicon carbide layer. A nitrogen concentration and a carbon concentration in a position 1 nm from the peak toward the silicon oxide layer is not more than 1&#xd7;10cm, and a nitrogen concentration in a position 1 nm from the peak toward the silicon carbide layer is not more than 1&#xd7;10cm.

Semiconductor device, semiconductor device manufacturing method, inverter circuit, driver device, vehicle, and elevator

A semiconductor device according to an embodiment includes: a silicon carbide layer; a silicon oxide layer; and a region disposed between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration equal to or more than 1&#xd7;10cm. A nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region have a peak in the region, a nitrogen concentration at a first position 1 nm away from the peak to the side of the silicon oxide layer is equal to or less than 1&#xd7;10cmand a carbon concentration at the first position is equal to or less than 1&#xd7;10cm, and a nitrogen concentration at a second position 1 nm away from the peak to the side of the silicon carbide layer is equal to or less than 1&#xd7;10cm.

According to an embodiment of the invention, a semiconductor device includes a base body that includes silicon carbide, a first semiconductor member that includes silicon carbide and is of a first conductivity type, and a second semiconductor member that includes silicon carbide and is of a second conductivity type. A first direction from the base body toward the first semiconductor member is along a [0001] direction of the base body. The second semiconductor member includes a first region, a second region, and a third region. The first semiconductor member includes a fourth region. A second direction from the first region toward the second region is along a [1-100] direction of the base body. The fourth region is between the first region and the second region in the second direction. A third direction from the fourth region toward the third region is along a [11-20] direction of the base body.

A semiconductor device according to embodiments includes a p-type SiC region, a gate insulating film disposed on the p-type SiC region, and a gate electrode disposed on the gate insulating film and including a p-type impurity and 3C&#x2014;SiC.

Semiconductor device and method for manufacturing the same

According to one embodiment, a method for manufacturing a silicon carbide base body is disclosed. The method can include preparing a first base body including silicon carbide. The first base body includes a first base body surface tilted with respect to a (0001) plane of the first base body. A first line segment where the first base body surface and the (0001) plane of the first base body intersect is along a [11-20] direction of the first base body. The method can include forming a first layer at the first base body surface. The first layer includes silicon carbide. The method can include removing a portion of the first layer. The first-layer surface is tilted with respect to a (0001) plane of the first layer. A second line segment where the first-layer surface and the (0001) plane of the first layer intersect is along a [&#x2212;1100] direction.

Method for manufacturing silicon carbide base body, method for manufacturing semiconductor device, silicon carbide base body, and semiconductor device

According to one embodiment, a semiconductor device includes a silicon carbide member, first, second, and third electrodes, and a first insulating member. The silicon carbide member includes first, second, and third silicon carbide regions. The first silicon carbide region includes first, second, third, and fourth partial regions. The third partial region is between the first and second partial regions. The fourth partial region is between the third partial region and the first electrode. The second silicon carbide region includes first and second semiconductor regions. The third silicon carbide region includes third and fourth semiconductor regions. The first insulating member includes first, second, and third insulating regions. The second electrode is electrically connected to the first silicon carbide region. The third and fourth partial regions are between the second and first electrodes. The third electrode is electrically connected to the second silicon carbide region.

A semiconductor device of an embodiment includes a first electrode, a second electrode, a silicon carbide layer between the first electrode and the second electrode, and the silicon carbide layer having a first plane and a second plane, the silicon carbide layer including a first trench, p-type first silicon carbide regions and n-type second silicon carbide regions alternately disposed, a p-type third silicon carbide region between the second silicon carbide region and the first plane, and an n-type fourth silicon carbide region between the third silicon carbide region and the first plane, and a p-type fifth silicon carbide region between the first silicon carbide region and the first trench, a gate electrode in the first trench, and a gate insulating layer. The length of the first silicon carbide region perpendicular to the first plane is longer than a depth of the first trench.

Growing community of inventors

Machida, Japan

Johji Nishio