Nxp B.v.

St-ericsson Sa

Koninklijke Philips Corporation N.v.

Stmicroelectronics International N.v.

Oct Circuit Technologies International Limited

Johannes Petrus Antonius Frambach

Paul Mateman

Cornelis Klaas Waardenburg

Sujan Pandey

Leonardus Hesen

Stefan Paul Van Den Hoek

Gerard Arie De Wit

Clemens Gerhardus Johannes De Haas

Petri Heliö

Roeland Heijna

Paavo Väänänen

Petri Korpi

Berend Hendrik Essink

Sjoerd Martijn Herder

Thomas John William Donaldson

Marko Van Houdt

Rinke De Jong

A transmitter circuit including an impedance setting circuit having first and second legs, wherein each leg includes an adjustable pull-up resistance and an adjustable pull-down resistance connected in series between a supply terminal and a reference terminal. A first-leg-node, between the adjustable resistances of the first leg, is connected to a first bus terminal. A second-leg-node, between the adjustable resistances of the second leg, is connected to a second bus terminal. The controller detects a transition in a transmission data signal, and in response to a dominant to recessive transition the controller controls a voltage setting circuit to set the differential driver voltage on the bus to a recessive value; adjusts each of the adjustable pull-up resistances and the adjustable pull-down resistances with the same target impedance profile such that the transmitter circuit drives the bus with a target driver impedance for an active recessive period of a bit time.

Transmitter circuit

An attenuation device for a CAN transceiver comprises two device output nodes configured to electrically couple the attenuation device via the device output nodes between two transceiver terminals of the CAN transceiver. The attenuation device is configured to change from a first device state to a second device state when a common mode voltage is applied to the device output nodes that is either greater than a first reference voltage or less than a second reference voltage that is less than the first reference voltage. The attenuation device causes a first electrical output resistance at each device output node during the first device state and causes a second electrical output resistance at each device output node during the second device state in which the second output resistance is less than the first output resistance.

Device for can transceiver, transceiver and method

A Controller Area Network (CAN) transmitter, in which transitions between output levels are smoothed through use of multiple Digital to Analog Converters (DACs) switched by a multi-phase clock signal. Example embodiments include a CAN transmitter () comprising: an oscillator () configured to generate a clock signal having n equally spaced phases (clk_0, clk_120, clk_240), where n is an integer greater than 1; n Digital to Analog Converters, DACs (-), each DAC having an input connected to one of the n phases of the clock signal and to a common data input line, each DAC being configured to provide an output signal that transitions between first and second output levels in M discrete steps upon being triggered by a transition of a signal on the data input line synchronized with the one of the n phases of the clock signal; and an output amplifier stage () configured to provide a differential CAN output signal from a combination of output signals from each of the n DACs (-).

Can transmitter

The present application relates to a circuit and a transceiver comprising the circuit. The circuit comprises two bus line terminals for coupling to a bus and a bridge circuit comprising two legs. Each leg comprises an adjustable pull resistance and an adjustable push resistance connected in series with a respective one of the two bus line terminals. The adjustable pull resistances and the adjustable push resistances of the bridge circuit enable to independently adjust a driver impedance and to independently adjust a differential driver voltage on the bus. The circuit may further comprise an edge detector is coupled to a transmit data input and configured to detect a transition on the transmit data input and to adjust the impedances of the adjustable pull resistances and the adjustable push resistances in response to the detected transition.

Transmitter with independently adjustable voltage and impedance

The present application relates to a transceiver, TX/RX PHY, and a method of operating the TX/RX PHY arranged for bi-directional data communication of a node with a counterpart node connected to in a point-to-point network using differential mode signaling over a single twisted-pair cable. A TX adjustment component is arranged in a TX path of the TX/RX PHY and configured to adjust a TX data communication signal generated by the TX/RX PHY for transmittal to the counterpart node. The TX adjustment component is further configured to accept information about a common mode signal detected on the single twisted-pair cable and to adjust the TX data communication signal to at least weaken the common mode signal occurring at the counterpart node in response to transmitting the TX data communication signal.

Transceiver and method of adjusting the TX signal of the transceiver for weakening EMI

A transceiver, TX/RX PHY, arranged for bi-directional data communication of a node with a counterpart node connected to a point-to-point network using differential mode signaling over a single twisted-pair cable is disclosed. The transceiver, TX/RX PHY, includes a common mode choke arranged between of the TX/RX PHY and the single twisted-pair cable and provided for common mode current suppression. Further included is a switching arrangement arranged between the TX/RX PHY, the common mode choke and the single twisted-pair cable and configured to switchably change a polarity of one of the windings of the common mode choke. A detection section is included and coupled via the switching arrangement to the common mode choke and configured to detect a common mode signal on the single twisted-pair cable in response to a transmission of a test signal by the counterpart node.

Electromagnetic emission detection, transceiver and system

A resistive/residual Charge to Digital Timer (RCDT) provides efficient, accurate measurement of short time delay between two signals, by converting the time delay to current, and measuring the charge integrated by a capacitor over a duration. In one embodiment, in quantizing this charge (measured as voltage), a residual charge is maintained cycle-to-cycle. This allows for implementation of a Noise shaping Charge to Digital Timer (NCDT), providing improved resolution over a plurality of measurement cycles. The RCDT/NCDT is particularly (but not exclusively) well suited for phase error detection in a Digital Phase Locked Loop.

Resistive/residue charge-to-digital timer

High-speed RF differential, Quadrature, divide-by-2 clock divider designs are based on inverters and clocking circuits connected in a serial ring formation. In one embodiment, only NMOS transistors are used in the inverters, and only PMOS transistors are used in the clocking circuits. This structure uses only 12 transistors. The input can be coupled directly to a VCO output, and provides minimum loading, as each VCO output is connected to only two transistors. Another embodiment comprises clocked inverter stages connected in a serial ring configuration with inverters between stages. The RF clock (or VCO signal) is used at the outer side of the inverters for speed improvement. In both circuits, positive and negative clock inputs are connected alternately at each stage of the ring.

High speed RF divider

An RF power amplifier for a polar transmitter converts an amplitude component signal into a 1-bit digital amplitude signal, which is fed to a digital finite impulse response filter. Successive taps of the filter each have an RF amplification stage arranged to amplify successively delayed versions of the 1-bit digital amplitude signal, the amplifying being according to a respective tap coefficient, and according to the RF carrier modulated by the phase component. The filter is arranged to combine the outputs of the taps to provide the amplified RF signal. The power amplifier uses a one bit stream which therefore has only two states (2 values), thus achieving linearity in principle. Device mismatch between taps does not lead to non-linearity or distortion.

RF amplifier with digital filter for polar transmitter

A sampler circuit comprises a plurality of series-connected sampler cells and a detector circuit. Each successive stage comprises twice the number of sampler cells, in parallel, as the previous stage, and is clocked at half the sampling frequency of the previous stage. Each sampler cell comprises two parallel branches of series-connected clocked inverters. A clocked inverter is operative to invert an applied signal during one phase of an applied sampling clock, and to render a high impedance output during the other sampling clock phase. Successive clocked inverters are clocked with opposite (i.e., positive/negative) versions of the sampling clock. The detector circuit examines the outputs of the last stage of sampler cells, and may for example comprise an OR function to detect a state transition in an applied input signal. The sampler circuit exhibits immunity to metastability and low power consumption.

Sampler circuit

A symmetrical, balanced, down-conversion mixer is achieved by the coordinated layout of a balanced Local Oscillator (LO) divider circuit and a balanced Radio Frequency (RF) mixer circuit, such that the LO divider is in the center and the RF mixer is arrayed symmetrically around the LO divider. In particular, the LO divider is partitioned into four portions (e.g., Ip, In, Qp, Qn), which are placed in respective quadrants, defined by orthogonal reference axes through the LO divider center. The RF mixer is similarly partitioned into four corresponding portions, which are placed around the LO divider portions in each quadrant. By integrating the LO divider and RF mixer in the layout of the symmetric, balanced, down-conversion mixer, greater component matching and control of current paths are possible, improving operational quality parameters such as IRR, IP, and LO feedthrough.

Mixer divider layout

High-speed RF differential, Quadrature, divide-by-2 clock divider designs are based on inverters and clocking circuits connected in a serial ring formation. In one embodiment, only NMOS transistors are used in the inverters, and only PMOS transistors are used in the clocking circuits. This structure uses only 12 transistors, The input can be coupled directly to a VCO output, and provides minimum loading, as each VCO output is connected to only two transistors. Another embodiment comprises clocked inverter stages connected in a serial ring configuration with inverters between stages. The RF clock (or VCO signal) is used at the outer side of the inverters for speed improvement. In both circuits, positive and negative clock inputs are connected alternately at each stage of the ring.

Disclosed is a frame synchronizing device and method for a binary data transmission system wherein digital data are transmitted as a serial bit stream organized into frames, each frame including a pre-defined frameheader, wherein said serial bit stream is inputted into a serial input portion of a serial input parallel output shift register means having at least as many stages as the number of bits of a frame, and said frames are outputted in a consecutive order from a parallel output portion of said shift register means. The particularity of the present invention is that it is detected whether or not a frameheader is present in the output of said parallel output portion, and, if not, the outputting of a frame from said parallel output portion is delayed by at least one time period which is needed for shifting a bit in said serial input portion from a stage to a next one, until synchronization is reached.

Frame synchronizing device and method

A digital phase locked loop (DPLL) operates in the frequency domain. The period (and hence frequency) of a reference frequency clock signal is determined by sampling with a (higher frequency) digitally controlled oscillator (DCO) clock. The period is compared to the period representation of a desired frequency, and the frequency error signal is integrated in a loop filter and applied as a control input to the DCO. To prevent spurious emissions resulting from the accumulation of quantization errors in the frequency determination and comparison operations, the arrival time of state transition edges of the reference frequency clock signal are randomized prior to sampling. The edge randomization control signal preferably has a triangular probability density function, and its spectrum has most significant energy outside the loop bandwidth of the DPLL; hence, the spurious emissions caused by the accumulation of quantization errors are filtered out by the loop filter.

Reference clock sampling digital PLL

An electronic circuit comprises a delay circuit that with a chain of saw tooth delay stages (-), coupled in a loop to form an oscillator for example. Each stage comprises an integrating circuit () and a current modulator () coupled to the integrating circuit (). Each stage triggers a transition in the next stage when the integration result reaches a level defined by a reference voltage. Correlating circuitry () is provided with current outputs to generate currents to the current modulators () and reference voltages for the saw tooth delay stages (-). The reference voltages are generated at least partly from a common reference (), so that noise in the currents from the current modulators () and reference voltages is correlated in a way that at least partly cancels the effect of the noise on the delay time.

Growing community of inventors

Nijmegen, Netherlands

Johannes Petrus Antonius Frambach