Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V.

Globalfoundries Inc.

Namlab Ggmbh

Globalfoundaries Inc.

Johannes Mueller

Patrick Polakowski

Dina Triyoso

Stefan Flachowsky

Maximilian Ludwig Drescher

Stefan Riedel

Stefan Mueller

Sanford Chu

Konrad Seidel

Robert Binder

Joachim Metzger

Mark Gerard Nolan

Wenke Weinreich

An illustrative device disclosed herein includes a semiconductor substrate. The substrate includes a source region, a drain region and a channel region. The channel region is arranged between the source region and the drain region. A gate insulation layer is provided over the channel region. A floating gate electrode is provided over the gate insulation layer. A layer of a ferroelectric material is provided over the floating gate electrode. A top electrode is provided over the layer of ferroelectric material. A projected area of the top electrode onto a plane that is perpendicular to a thickness direction of the semiconductor substrate is smaller than a projected area of the floating gate electrode onto the plane.

Device including a floating gate electrode and a layer of ferroelectric material and method for the formation thereof

The invention relates to a method for manufacturing a microelectronic circuit. A substrate is provided. A source contact, a bulk contact and a drain contact are each produced for a transistor and for a memory transistor. In a respective common step, an insulating layer of the transistor and an insulating layer of the memory transistor as well as a metal layer of the transistor and a metal layer of the memory transistor are produced. At least one capacitor is produced as part of the memory transistor. Gate contacts connected to the metal layer of the transistor and connected to a metal layer of the capacitor of the memory transistor, respectively, are produced. Furthermore, the invention relates to a microelectronic circuit.

Method for manufacturing a microelectronic circuit and corresponding microelectronic circuit

A method disclosed herein includes providing a semiconductor structure, the semiconductor structure comprising a semiconductor substrate and a gate stack, the gate stack comprising a gate insulation material over the substrate, a floating gate electrode material over the gate insulation material, a ferroelectric transistor dielectric over the floating gate electrode material and a top electrode material over the ferroelectric transistor dielectric, performing a first patterning process to remove portions of the top electrode material and the ferroelectric transistor dielectric and performing a second patterning process after the first patterning process to remove portions of the floating gate electrode material and the gate insulation material, wherein a projected area of an upper portion of the gate structure onto a plane that is perpendicular to a thickness direction of the substrate is smaller than a projected area of the lower portion of the gate structure onto the plane.

Method of forming a device including a floating gate electrode and a layer of ferroelectric material

An illustrative method disclosed herein includes providing a semiconductor structure. The semiconductor structure includes a first interlayer dielectric provided over a semiconductor substrate. A first electrode of a first capacitor is formed over the first interlayer dielectric. A layer of first dielectric material is deposited over the first electrode of the first capacitor and the first interlayer dielectric. A layer of electrically conductive material is deposited over the layer of first dielectric material. A second electrode of the first capacitor and a first electrode of the second capacitor are formed from the layer of electrically conductive material. After the formation of the second electrode of the first capacitor and the first electrode of the second capacitor, a layer of second dielectric material is deposited and a second electrode of the second capacitor is formed over the layer of second dielectric material.

Semiconductor structure including capacitors having different capacitor dielectrics and method for the formation thereof

Nonvolatile storage with long memory endurance having the advantages of easy manufacturability is obtained by using a memory cell having an information storage element including a ferroelectric material, and operating the memory cell in a volatile operating mode and a nonvolatile operating mode. The option of operating the memory cell in the volatile operating mode enables the associated advantages of high memory speed at long endurance, wherein, however, the option of operating the memory cell in the nonvolatile operating mode can bridge gaps in the power supply.

Memory cell

The present disclosure provides integrated circuit elements and MIM/MIS capacitors having high capacitance and methods of forming according integrated circuit elements and integrated MIM/MIS capacitors and methods of controlling an integrated circuit element and an integrated MIM/MIS capacitor. In various aspects, a substrate is provided and a dielectric layer or insulating layer is formed over the substrate. Furthermore, an electrode layer is disposed over the dielectric layer or insulating layer. Herein, the dielectric layer or insulating layer is in an antiferroelectric phase. In various illustrative embodiments, the integrated circuit element may implement a MOSFET structure or a capacitor structure.

Complex circuit element and capacitor utilizing CMOS compatible antiferroelectric high-k materials

The present disclosure provides a semiconductor device comprising a substrate, an undoped HfOlayer formed over the substrate and a TiN layer formed on the HfOlayer. Herein, the undoped HfOlayer is at least partially ferroelectric. In illustrative methods for forming a semiconductor device, an undoped amorphous HfOlayer is formed over a semiconductor substrate and a TiN layer is formed on the undoped amorphous HfOlayer. A thermal annealing process is performed for at least partially inducing a ferroelectric phase in the undoped amorphous HfOlayer.

Growing community of inventors

Dresden, Germany

Johannes Mueller