Globalfoundries Inc.

Advanced Micro Devices Corporation

Johannes M Van Meer

Yanxiang Liu

Scott D Luning

Michael John Hargrove

Manfred Eller

Srikanth Balaji Samavedam

Jerome Ciavatti

Gen Pei

Christian Gruensfelder

Huicai Zhong

Frank Wirbeleit

Tibor Bolom

Xiaodong Yang

Cuiqin Xu

Isabelle Ferain

Approaches for enabling epitaxial growth of silicon fins in a device (e.g., a fin field effect transistor device (FinFET)) are provided. Specifically, approaches are provided for forming a set of silicon fins for a FinFET device, the FinFET device comprising: a set of gate structures formed over a substrate, each of the set of gate structures including a capping layer and a set of spacers; an oxide fill formed over the set of gate structures; a set of openings formed in the device by removing the capping layer and the set of spacers from one or more of the set of gate structures; a silicon material epitaxially grown within the set of openings in the device and then planarized; and wherein the oxide fill is etched to expose the silicon material and form the set of fins.

Epitaxially forming a set of fins in a semiconductor device

A CMOS circuit is provided that includes a PMOS transistor, an NMOS transistor adjacent the PMOS transistor in a channel width direction, a compressive stress liner overlying the PMOS transistor, and a tensile stress liner overlying the NMOS transistor. A portion of the compressive stress liner and a portion of the tensile stress liner are in a stacked configuration, and an overlap region of the compressive stress liner and the tensile stress liner is sufficient to result in an enhanced transverse stress in the compressive stress liner or the tensile stress liner.

CMOS circuit having a tensile stress layer overlying an NMOS transistor and overlapping a portion of compressive stress layer

One illustrative method disclosed herein includes, among other things, performing a source/drain extension ion implantation to form a doped extension implant region in the source/drain regions of the device, performing an ion implantation process on the source/drain regions with a Group VII material (e.g., fluorine), after performing the Group VII material ion implantation process, forming a capping material layer above the source/drain regions, and, with the capping material layer in position, performing an anneal process so as to form stacking faults in the source/drain regions.

Stress memorization techniques for transistor devices

One illustrative device disclosed herein includes a plurality of source/drain regions positioned in an active region on opposite sides of a gate structure, each of the source/drain regions having a lateral width in a gate length direction of the transistor and a plurality of halo regions, wherein each of the halo regions is positioned under a portion, but not all, of the lateral width of one of the plurality of source/drain regions. A method disclosed herein includes forming a plurality of halo implant regions in an active region, wherein an outer edge of each of the halo implant regions is laterally spaced apart from an adjacent inner edge of an isolation region.

Transistor device with improved source/drain junction architecture and methods of making such a device

A semiconductor structure with an improved shallow trench isolation (STI) region and method of fabrication is disclosed. The STI region comprises a lower portion filled with oxide and an upper portion comprising a high Young's modulus (HYM) liner disposed on the lower portion and trench sidewalls and filled with oxide. The HYM liner is disposed adjacent to source-drain regions, and serves to reduce stress relaxation within the shallow trench isolation (STI) oxide, which has a relatively low Young's modulus and is soft. Hence, the HYM liner serves to increase the desired stress imparted by the embedded stressor source-drain regions, which enhances carrier mobility, thus increasing semiconductor performance.

Shallow trench isolation

One illustrative method disclosed herein involves forming an integrated circuit product comprised of first and second N-type transistors formed in and above first and second active regions, respectively. The method generally involves performing a common threshold voltage adjusting ion implantation process on the first and second active regions, forming the first and second transistors, performing an amorphization ion implantation process to selectively form regions of amorphous material in the first active region but not in the second active region, after performing the amorphization ion implantation process, forming a capping material layer above the first and second transistors and performing a re-crystallization anneal process to convert at least portions of the regions of amorphous material to a crystalline material. In some cases, the capping material layer may be formed of a material having a Young's modulus of at least 180 GPa.

Methods of forming multiple N-type semiconductor devices with different threshold voltages on a semiconductor substrate

A method for forming raised source and drain regions in a semiconductor manufacturing process employs double disposable spacers. A deposited oxide is provided between the first and second disposable spacers, and serves to protect the gate electrode, first disposable spacers and a cap layer during the dry etching of the larger, second disposable spacers. Mouse ears are thereby prevented, while the use of a second disposable spacer avoids shadow-effects during halo ion-implants.

Raised source and drain process with disposable spacers

A stress enhanced CMOS circuit and methods for its fabrication are provided. One fabrication method comprises the steps of forming an NMOS transistor and a PMOS transistor adjacent the NMOS transistor in a channel width direction, the PMOS transistor and the NMOS transistor separated by an isolation region. A compressive stress liner is deposited overlying the transistors and the isolation region and is etched to remove the compressive stress liner from the NMOS transistor and from a portion of the isolation region. A tensile stress liner is deposited overlying the transistors, the isolation region, and the compressive stress liner and is etched to remove a portion of the tensile stress liner overlying a portion of the compressive stress liner and to leave the tensile stress liner overlying the NMOS transistor, the isolation region, and a portion of the compressive stress liner.

Stress enhanced CMOS circuits and methods for their fabrication

Methods are provided for semiconductor devices having low contact resistance. The method in accordance with one embodiment of the invention comprises forming an insulating layer overlying a semiconductor substrate, the semiconductor substrate having a device region therein. An opening is formed through the insulating layer to expose a portion of the device region, and the portion of the device region is then electrically contacted by a metallic liner layer. To reduce the resistance of the liner layer and hence the contact, ions of a conductivity determining impurity are implanted into the metallic liner layer. A metal layer is then deposited overlying the metallic liner layer to fill the opening through the insulating layer and to form a conductive plug.

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Newburgh, NY, United States of America

Johannes M Van Meer