Infineon Technologies Ag

Qimonda Ag

Giesecke+devrient Mobile Security Gmbh

Giesecke & Devrient Gmbh

Johannes Luyken

Franz Hofmann

Franz Kreupl

Thomas Schulz

Klaus Finkenzeller

Thomas Tarantino

Michael Specht

Michael Baldischweiler

Erhard Landgraf

Karlheinz Mayer

Wolfgang Rösner

Ulrich Huber

Claus Dietze

Wolfgang Hönlein

Johannes Kretz

Karl Eglof Hartel

Andrew Graham

Ralf Schedel

Jens Rudolph

Lars Dreeskornfeld

Andreas Morawietz

Hermann Sterzinger

Daniel Albert

Martin Städele

Volker Gerstenberger

Frank Schäfer

Helmut Schuster

Sebastian Wallner

A method is provided for installing a security-relevant portion of an application made available by an application provider in a security element of a terminal. The terminal requests the application from the application provider and receives the application. Subsequently, the received security-relevant portion of the application is transmitted to a trustworthy instance administrating the security element. The trustworthy instance subsequently installs the security-relevant portion of the application in the security element.

Method for installing security-relevant applications in a security element of a terminal

A semiconductor memory device comprises a plurality of memory cells, each memory cell having a respective transistor. The transistor comprises a transistor body of a first conductivity type, a drain area and a source area each having a second conductivity type, wherein said drain area and source area are embedded in the transistor body on a first surface of said transistor body, a gate structure having a gate dielectric layer and a gate electrode. Said gate structure is arranged between said drain area and said source area. An emitter area of said first conductivity type is provided wherein said emitter area is arranged on top of said drain area.

Semiconductor memory device

The invention relates to a vertical integrated component, a component arrangement and a method for production of a vertical integrated component. The vertical integrated component has a first electrical conducting layer, a mid layer, partly embodied from dielectric material on the first electrical conducting layer, a second electrical conducting layer on the mid layer and a nanostructure integrated in a through hold introduced in the mid layer. A first end section of the nanostructure is coupled to the first electrical conducting layer and a second end section is coupled to the second electrical conducting layer. The mid layer includes a third electrical conducting layer between two adjacent dielectric partial layers, the thickness of which is less than the thickness of at least one of the dielectric partial layers.

Vertically integrated field-effect transistor having a nanostructure therein

The present invention provides a FinFET transistor arrangement produced using a method with the steps: providing a substrate (); forming an active region () on the substrate a fin-like channel region (&#x2033;). Formation of the fin-like channel region (&#x2033;) has the following steps: forming a hard mask (S-S) on the active region (); anisotropic etching of the active region () using the hard mask (S-S) forming STI trenches (G-G) having an STI oxide filling (); polishing-back of the STI oxide filling (); etching-back of the polished-back STI oxide filling (); selective removal of components of the hard mask forming a modified hard mask (S-S); anisotropic etching of the active region () using the modified hard mask (S-S) forming widened STI trenches (G-G'), the fin-like channel regions (&#x2033;) of the active region () remaining for each individual FinFET transistor.

Production method for a FinFET transistor arrangement, and corresponding FinFET transistor arrangement

The invention relates to a method for fabricating stacked non-volatile memory cells. Further, the invention relates to stacked non-volatile memory cells. The invention particularly relates to the field of non-volatile NAND memories having non-volatile stacked memory cells. The stacked non-volatile memory cells are formed on a semiconductor wafer, having a bulk semi-conductive substrate and an SOI semi-conductive layer and are arranged as a bulk FinFET transistor and an SOI FinFet transistor being arranged on top of the bulk FinFET transistor. Both the FinFET transistor and the SOI FinFet transistor are attached to a common charge-trapping layer. A word line with sidewalls is arranged on top of said patterned charge-trapping layer and a spacer oxide layer is arranged on the sidewalls of said word line.

Non-volatile memory cells and methods for fabricating non-volatile memory cells

An array of charge-trapping memory cells and pluralities of parallel wordlines and parallel bitlines running transversely to the wordlines are arranged on a substrate surface. Gate electrodes are located between the wordlines and bitlines and are, in their sequence along the direction of the wordlines, connected alternatingly to one of two adjacent wordlines.

Semiconductor memory device and method of production

Growing community of inventors

Munich, Germany

Johannes Luyken