Nxp B.v.

Johannes J T M Donkers

Philippe Meunier-Beillard

Erwin Hijzen

Francois Neuilly

Sebastien Nuttinck

Guillaume Boccardi

Mark C J C M Kramer

Wibo Daniel Van Noort

Stefaan Decoutere

Stefaan Van Huylenbroeck

Joost Melai

Guillaume L R Boccardi

Li Jen Choi

Philippe Meunier-Bellard

Rafael Venegas

Greja J A M Verhelijden

Arturo Sibaja-Hernandez

Hijzen Erwin

Melai Joost

Wibo D Van Noort

François Neuilly

The invention relates to a semiconductor device () comprising a substrate (), a semiconductor body () comprising a bipolar transistor that comprises a collector region (), a base region (), and an emitter region (), wherein at least a portion of the collector region () is surrounded by a first isolation region (), the semiconductor body () further comprises an extrinsic base region () arranged in contacting manner to the base region (). In this way, a fast semiconductor device with reduced impact of parasitic components is obtained.

Gringo heterojunction bipolar transistor with a metal extrinsic base region

A semiconductor device () comprising a bipolar transistor and a field effect transistor within a semiconductor body () comprising a projecting mesa () within which are at least a portion of a collector region (and) and a base region () of the bipolar transistor. The bipolar transistor is provided with a first insulating cavity () provided in the collector region (and). The base region () is narrower in the plane of the substrate than the collector region (and) due to a second insulating cavity () provided around the base region () and between the collector region (and) and the emitter region (). By blocking diffusion from the base region the first insulating cavity () provides a reduction in the base collector capacitance and can be described as defining the base contact.

Semiconductor device and method of manufacture thereof

A method of manufacturing a MEMS device comprises forming a MEMS device element (). A sacrificial layer () is provided over the device element and a package cover layer () is provided over the sacrificial layer. The sacrificial layer is removed using at least one opening () in the cover layer and the at least one opening () is sealed by an anneal process.

MEMS devices

A semiconductor device () comprising a bipolar transistor and a fieldeffect transistor within a semiconductor body () comprising a projecting mesa () within which are at least a portion of a collector region (and) and a base region () of the bipolar transistor. The bipolar transistor is provided with an insulating cavity () provided in the collector region (and). The insulating cavity () may be provided by providing a layer () in the collector region (), creating an access path, for example by selectively etching polysilicon towards monocrystalline, and removing a portion of the layer () to provide the cavity using the access path. The layer () provided in the collector region may be of SiGe:C. By blocking diffusion from the base region the insulating cavity () provides a reduction in the base collector capacitance and can be described as defining the base contact.

Methods for manufacturing a bipolar transistor semiconductor device are described, along with devices fabricated in accordance with the methods. The methods include the steps of forming a stack of layers over a semiconductor body comprising a window definition layer (), a layer () of semiconductor material, a first insulating layer (), and a second insulating layer () which is selectively etchable with respect to the first insulating layer. A trench () is then etched into the stack down to the window definition layer. The portion of the trench extending through the second insulating layer is widened to form a wider trench portion () therethrough. A window () is defined in the window definition layer which is aligned with the wider trench portion, and serves to define the base-collector or base-emitter junction in the finished device.

Method of manufacturing a bipolar transistor semiconductor device and semiconductor devices obtained thereby

The invention relates to a method according to the part of the surface of the semiconductor body adjoining the opening and which is to be kept free is provided with a cover layer after which the high-crystalline layer is formed by means of a deposition process. The material of the cover layer can then easily be chosen such that it can be selectively etched relative to the silicon underneath. In addition, the cover layer can easily be selectively deposited on the relevant part of the surface because use can be made of an anisotropic deposition process. In such a process the cover layer is not deposited in the hollow and on the bottom of the hollow. It will be apparent that for the high-crystalline layer also other materials can be chosen such as SiGe having such low Ge contents that the SiGe cannot be etched selectively very well compared to the Silicon.

Method of manufacturing a bipolar transistor and bipolar transistor obtained therewith

The invention provides for an alternative and less complex method of manufacturing a bipolar transistor comprising a field plate () in a trench () adjacent to a collector region (), which field plate () employs a reduced surface field (Resurf) effect. The Resurf effect reshapes the electric field distribution in the collector region () such that for the same collector-base breakdown voltage the doping concentration of the collector region () can effectively be increased resulting in a reduced collector resistance and hence an increased bipolar transistor speed. The method comprises a step of forming a base window () in a first base layer () thereby exposing a top surface of the collector region () and a part of an isolation region (). The trench () is formed by removing the exposed part of the isolation region (), after which isolation layers () are formed on the surface of the trench (). A second base layer () is formed on the isolation layer (), thereby forming the field plate (), on the top surface of the collector region (), thereby forming a base region (), and on a sidewall of the first base layer (), thereby forming an electrical connection between the first base layer (), the base region () and the field plate (). An emitter region () is formed on a top part of the base region (), thereby forming the Resurf bipolar transistor.

Method of manufacturing a bipolar transistor

A method of manufacturing a bipolar transistor is compatible with FinFET processing. A collector region () is formed and patterned, base contact regions () formed on either side, and a gap formed between the base contact region. A base (), spacers () and an emitter () are formed in the gap.

Method of making bipolar transistor

The invention relates to a semiconductor device () with a substrate () and a semiconductor body () of silicon comprising a bipolar transistor with an emitter region, a base region and a collector region () first conductivity type, a second conductivity type opposite to said first conductivity type and the first conductivity type, respectively, with a first semiconductor region () comprising the collector region or the emitter region being formed in the semiconductor body (), on top of which a second semiconductor region () comprising the base region is present, on top of which a third semiconductor region () comprising the other of said collector region and said emitter region is present, said semiconductor body () being provided with a constriction at the location of the transition between the first and the second semiconductor region (), which constriction has been formed by means of an electrically insulating region () buried in the semiconductor body (). According to the invention a part of the semiconductor body that is formed above the buried electrically insulating region () is monocrystalline. This enables a strong lateral miniaturization of the device and results in excellent high frequency properties of the transistor. Such a device () is possible thanks to its manufacture with a method of manufacturing according to the invention.

Bipolar transistor having a second, base-comprising region consisting of a first layer, a second, constrictive, layer, and a third layer

The invention provides a method for fabricating a heterojunction bipolar transistor with a base connecting region (), which is formed self-aligned to a base region () without applying photolithographic techniques. Further, a collector connecting region () and an emitter region () are formed simultaneously and self-aligned to the base connecting region () without applying photolithographic techniques.

Method of fabricating a heterojunction bipolar transistor

A method of fabricating a bipolar transistor in a first trench () is disclosed wherein only one photolithographic mask is applied which forms a first trench () and a second trench (). A collector region () is formed self-aligned in the first trench () and the second trench (). A base region () is formed self-aligned on a portion of the collector region (), which is in the first trench (). An emitter region () is formed self-aligned on a portion of the base region (). A contact to the collector region () is formed in the second trench () and a contact to the base region () is formed in the first trench (). The fabrication of the bipolar transistor may be integrated in a standard CMOS process.

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Valkenswaard, Netherlands

Johannes J T M Donkers