Nxp B.v.

Koninklijke Philips Corporation N.v.

Integrated Device Technology, Inc.

Nxp Usa, Inc.

Johannes Hubertus Antonius Brekelmans

Gerben Willem De Jong

Lucien Johannes Breems

Muhammed Bolatkale

Robert Rutten

Shagun Bajoria

Jan Van Sinderen

Nenad Pavlovic

Manfred Zupke

Johannes O Voorman

Martin Kessel

Hendrik Van Der Ploeg

Dennis Jeurissen

Bernard Burdiek

Jan Niehof

Josephus Arnoldus Henricus Maria Kahlman

Erwin Janssen

Massimo Ciacci

Dave Willem Van Goor

Jozef Reinerus Maria Bergervoet

Hugo Veenstra

Konstantinos Doris

Godefridus Adrianus Maria Hurkx

Rachid El Waffaoui

Marc Godfriedus Marie Notten

Evert-Jan Pol

Frank Harald Erich Ho Chung Leong

Johan Frederik Witte

Alan Chin Leong Yeo

Olivier Crand

Reinier Hoogendoorn

Han Leng Paxton Tan

Albertus Willibrordus Oude Essink

Soheil Bahrami

Simon W K Lee

A digital conversion system including a sigma-delta converter, a tone generator that generates injects a tone signal into the conversion path of the sigma-delta converter at a frequency that is outside operating signal frequency range, a tone detector that isolates and detects a level of the injected tone signal and provides a corresponding tone level value, a tone ratio comparator that converts the tone level value into a tone level ratio and that compares the converted tone level ratio with an expected tone level ratio to provide an error signal, and a loop controller that converts the error signal to a correction signal to adjust a loop filter frequency the sigma-delta converter. Tones may be serially injected one at a time or simultaneously in parallel for determining a measured tone level ratio for comparison with a corresponding one of multiple stored expected tone level ratios.

System and method of calibration of sigma-delta converter using tone injection

A digital conversion system including a sigma-delta converter, a signal generator providing a substantially symmetrical injection signal that is injected into the sigma-delta converter conversion path, bandpass filters for filtering the injection signal and the output of the sigma-delta converter, a correlator that correlates the filtered signals for providing an error signal, and a loop controller that uses the error signal to adjust a resonant frequency of the sigma-delta converter to output a target notch frequency. The loop controller may adjust a resonant frequency of a loop filter of the sigma-delta converter, in which the bandpass filters may each be centered at the target notch frequency at the output of the sigma-delta converter. The correlator may include a complex conjugate block, a multiplier and a mean calculator. The loop controller may include a converter and an amplifier and an integrator or a least-mean square block.

System and method of calibration of sigma-delta converter using injected signal correlation

An apparatus including analog-to-digital conversion (ADC) circuitry is disclosed. The apparatus includes a plurality of comparators susceptible to offset variation and a shuffler circuit configured to shuffle input sources to the respective comparators. Feedback circuitry is also included and is configured and arranged with the ADC circuitry to detect offset variation in the outputs of each comparators for the shuffled inputs, relative to outputs of the plurality of comparators and compensate for the offset variation in the comparators based on the offset differences between the respective comparators.

Offset compensation in ADC circuitry

Aspects of the disclosure are directed to compensating for errors in in an analog-to-digital converter circuit (ADC). As may be implemented in accordance with one or more embodiments, an apparatus and/or method involves an ADC that converts an analog signal into a digital signal using an output from a digital-to-analog converter circuit (DAC). A compensation circuit generates a compensation output by, for respective signal portions provided to the DAC, generating a feedback signal based on an incompatibility between the conversion of the signal portions into an analog signal and the value of the signal portions provided to the DAC. A compensation output is generated based on the signal input to the DAC with a gain applied thereto, based on the feedback signal.

Signal processing and conversion

A processor is disclosed. The processor includes a first-receiver-node for receiving a first-receiver-signal, a second-receiver-node for receiving a second-receiver-signal, a first-output-node for coupling to a digital-baseband-processor, a second-output-node for coupling to the digital-baseband-processor and a first-active-data-pipe extending between the first-receiver-node and the first-output-node. The first-active-data-pipe includes a first-analog-to-digital-converter comprising a first-ADC-input coupled to the first-receiver-node and a first-ADC-output coupled to the first-output-node. The first-analog-to-digital-converter is configured to provide a first-digital-signal to the first-output-node. The processor comprises a first-reference-node and a configurable-data-pipe extending between the second-receiver-node and the second-output-node.

Data processor

Corrections are provided for mismatches between an in-phase (I) signal and a quadrature-phase (Q) signal, the I and Q signals having a first frequency band. A frequency filter circuit filters the I and Q signals to produce a filtered I and Q output with a second frequency band that is a subset of the first frequency band. Digital circuitry includes a multiple-tap correction filter having a plurality of taps and configured to generate I and Q output signals by filtering the I and Q signals according to respective sets of coefficients for the plurality of taps. A coefficient estimator generates the sets of coefficients relative to different frequency bands.

Multiple-tap compensation and calibration

Embodiments of variable gain transimpedance amplifiers are described. In an embodiment, the variable gain transimpedance amplifier may include an amplifier coupled to an adjustable gain feedback network, the adjustable gain feedback network including a selectable set of Resistor-Capacitor (RC) branches, each RC branch having one or more unit RC elements, each unit RC element being comprised of a unit resistor and a unit capacitor arranged in parallel.

Variable gain transimpedance amplifier

The invention relates to frequency conversion systems, in particular for use as up-converters or down-converters in radiofrequency (RF) receivers or transmitters, exemplary embodiments including a radiofrequency receiver including an RF signal input; a mixing module including a first plurality of IF amplifiers each connected to the RF signal input via a switch; a multi-phase local oscillator signal generator configured to provide a switching signal to each switch; and a summing module configured to receive output signals from each of the IF amplifiers and to provide a second plurality of output IF signals from a weighted sum of the IF amplifier output signals, wherein the second plurality is different to the first plurality.

Conversion system

An oscillator circuit comprising first and second resonator terminals for connecting to respective terminals of a resonator. The oscillator circuit also comprises a first inverting amplifier connected between the first and second resonator terminals in a first mode of operation; and a back to back pair of second inverting amplifiers connected between the first and second resonator terminals in a second mode of operation. There is also provided a controller configured to compare an operational parameter of the oscillator circuit to a switchover threshold, and switch the oscillator circuit from the first mode of operation to the second mode of operation when the operational parameter exceeds the switchover threshold.

Oscillator circuit

An electronic device comprising a passive harmonic-rejection mixer () and a calibration circuitry (). The passive harmonic rejection mixer has an input () connected to several sub-mixer stages (), and the sub-mixer stages are connected to a summing module () for generating the output (). Each sub-mixing stage comprises a gating module (), an amplifier (), and a weighting module (), the gating module selectively passing the input signal or the input signal with inverted polarity under the control of control signals. The calibration circuitry () is adapted to input a reference signal () to the input of the mixer, receive an output signal () from the output of the mixer, and set the weights (K, K, K, K) of the weighting modules to make the output signal match an expected output signal.

Calibration of passive harmonic-rejection mixer

The invention relates to a digital signal generator for providing one or more phases of a local oscillator signal for use in digital to analogue converters and harmonic rejection mixers. Embodiments disclosed include a local oscillator signal generator () for a mixer of a radiofrequency receiver, the signal generator () comprising a bit sequence generator () having a plurality of parallel output lines (), a digital signal generator () having a serial output line () and a plurality of input lines connected to respective output lines () of the bit sequence generator () and a clock signal input line (), wherein the digital signal generator () is configured to provide an output bit sequence on the serial output line () at a rate given by a clock signal provided on the clock signal input line () and a sequence given by a sequence of bits from the bit sequence generator () on the plurality of input lines ().

Digital signal generator

A signal processing arrangement comprises a series of latches (XDL, L, L) arranged as a clocked delay line (CDL) having a data input and a data output that are coupled to each other so as to form an inverting loop. An enable circuit (ACDL) allows or prevents a latch (L) in the series of latches from changing state depending on whether, one clock cycle ago, the latch concerned received a given binary value or the inverse of that given binary 5 value, respectively, from the preceding latch (L) in the series of latches. Such a circuit configuration allows a low-cost frequency division by an odd number with relatively small duty cycle errors.

Signal processing arrangement

A signal processing arrangement comprises an amplifier (AMP V) that includes a stage with complementary transistors (MP, MN) of opposite conductivity type arranged in series between two supply lines (+, &#x2212;). A controllable biasing circuit (CCS) is provided for changing a quiescent operating point of the stage as a function of a control signal (CS). A control arrangement measures an even order 5 distortion of the amplifier (AMP V) and adjusts the control signal (CS) so that the even order distortion is below a critical level.

Arrangement for calibrating the quiescent operating point of a push-pull amplifier

A device for receiving a RF signal () with loop-through output () is provided. The device comprises: an input () receiving a RF input signal (); an analog-digital converter () converting the RF input signal () to a digital signal (); a digital signal processing unit () digitally processing the digital signal (); a digital-analog converter () converting the processed digital signal () to a loop-through RF signal () corresponding to the RF input signal (); and a loop-through output () outputting the loop-through RF signal ().

Device for receiving a RF signal with loop-through output and method for looping a RF input signal through a device for receiving RF signals

A frequency conversion circuit configured to mix a first input signal (RF+,RF&#x2212;) at a first frequency with a second input signal (LO+,LO&#x2212;) at a second frequency to provide an output intermediate frequency signal (IF), the circuit comprising: first and second mixing modules, each mixing module comprising a voltage to current converter configured to receive the first input signal (RF+,RF&#x2212;) and connected to a Gilbert mixer configured to receive the second input signal (LO+,LO&#x2212;); an intermediate frequency output circuit having inputs connected to receive an intermediate frequency current signal (IF+,IF&#x2212;) from outputs of each of the Gilbert mixers and an output configured to provide the output intermediate frequency voltage signal (IF), wherein the first and second mixing modules comprise transistors which are complementary to each other.

Growing community of inventors

Nederweert, Netherlands

Johannes Hubertus Antonius Brekelmans