Texas Instruments Corporation

Texas Instruments Incorporated Deutschland, Gmbh

Johannes Gerber

Matthias Arnold

Frank Dornseifer

Bernhard Ruck

Ruediger Kuhn

Asif Qaiyum

Vadim Valerievich Ivanov

Santiago Iriarte Garcia

Korbinian Huber

Ralf Peter Brederlow

Volker Rzehak

Ronald Nerlich

Christian Sichert

Fraj Gharib

Bernhard Wolfgang Ruck

A system includes a digital controller in a voltage regulator. The system also includes a passgate array including two or more passgate transistors, where the passgate array is configured to provide a load current to a load, and where the digital controller is configured to activate and deactivate each passgate transistor in the passgate array. The system also includes a feedback loop configured to provide an error signal to the digital controller, the error signal based on a difference between an output voltage of the voltage regulator and a programmed voltage for the voltage regulator. The digital controller is configured to activate or deactivate a passgate transistor based at least in part on the error signal. The digital controller is also configured to activate at least one passgate transistor and deactivate at least one passgate transistor responsive to a clock cycle.

Digital LDO passgate rotation

An integrated circuit is provided with a bandgap voltage reference circuit having a bandgap reference voltage output. A bandgap failure detection circuit is coupled to the bandgap reference voltage output. The bandgap failure detection forms a model value of the reference voltage from a first time, compares a present value of the reference voltage at a second time to the model value; and asserts a bandgap fail signal to indicate when the present value is less than the model value by a threshold value. The integrated circuit is reset by the bandgap fail signal. The detection circuit may be operated from a failsafe voltage domain that also allows a critical circuit to complete a pending operation during a reset.

Bandgap reference voltage failure detection

An electronic device that includes a power on reset, a variable power supply filter coupled to the power on reset, and control logic coupled to the power on reset and the variable power supply filter. The control logic is configured to activate the variable power supply filter based on a core domain of the electronic device being active.

Adaptive system controlled power supply transient filter

A power-gated electronic device and a method of operating the same is provided. The power-gated electronic device comprises a low drop out voltage power supply (LDO), an auxiliary power supply and at least one electronic domain having a power gate. The LDO provides a supply voltage to the at least one electronic domain which is coupled to a supply rail of the LDO via a switch, acting as a power gate. The auxiliary power supply comprises at least one current source which is coupled to the electronic domain via an auxiliary switch acting as an auxiliary power gate. The auxiliary power supply is configured to control the auxiliary switch as a function of a voltage difference between a reference voltage and the auxiliary supply voltage.

Power-gated electronic device

A dual-comparator circuit includes a main comparator providing a first decision output (outmain) including a main MOS differential pair, and an auxiliary comparator including an auxiliary MOS differential pair providing a second decision output (outaux). The auxiliary comparator receives a differential input voltage (Vin), and generates a control signal that is coupled to an enable input of the main comparator. A first operating mode (OM) is implemented when |Vin|&#x3c;a predetermined voltage level (PVL), where the control signal activates the main comparator. A second OM is implemented when |Vin|&#x2267;PVL where the main differential pair is protected by a switch from developing transient voltage input offset (VIO). Logic circuitry has logic inputs receiving outaux and outmain, and a logic output providing a decision result for the dual-comparator circuit using outmain when in the first OM and outaux when in the second OM.

Dual-comparator circuit with dynamic VIO shift protection

A mixed signal approach is applied to detect an output voltage condition as applied to a load. A current mode monitoring approach can be adopted and applied in discrete time using a mixed analog and digital approach. For application to various low drop-out voltage regulator situations, a sensing transistor can be connected in parallel with a feedback loop transistor of the low drop-out voltage regulator circuit to create a sensing current that is proportional to the current passing through the feedback loop transistor and thus the output current provided to the load. This sensing approach can be adapted to sense both overload and light load conditions to allow dynamic power control of the device.

Control for voltage regulators

A bandgap reference (BGR) startup verification circuit includes a current minor for receiving an output current from a bandgap reference (BGR) circuit and generating output currents therefrom. A first verification sub-circuit is coupled to receive a first output current to generate a detection voltage (Vdet) and includes a voltage comparator receiving Vdet and a voltage output of the BGR circuit (VBG) to provide a first verification output. A second verification sub-circuit including a voltage comparator is coupled to receive a second output current and a second reference current and provide a second verification output. A third verification sub-circuit includes a current comparator coupled to receive a third output current and a third reference current and provide a third verification output. A digital state machine has inputs receiving the first, second and third verification output, and circuitry for processing these outputs to determine whether the BGR circuit has properly started.

Verification of bandgap reference startup

An electronic device includes an integrated circuit with a FRAM memory and an integrated capacitor connected between a power supply for the FRAM memory and ground. The integrated capacitor has a capacitance sufficient to store the charge necessary for a complete read-and-write-back cycle of the FRAM memory. When granting read-access to the FRAM memory, the FRAM memory is supplied by the integrated capacitor which is then disconnected from the integrated circuit power supply. Upon receiving a request for a read-access to the FRAM memory, a charge detector detects whether the internal capacitor is sufficiently charged for a complete read-and-write-back cycle of the FRAM memory. Read-access to the FRAM memory is only granted if the internal capacitor is sufficiently charged and disconnected from the power supply. An alternative embodiment alternately charges and powers the FRAM from two integrated capacitors.

Integrated circuit comprising a FRAM memory and method for granting read-access to a FRAM memory

An electronic device includes a bandgap reference voltage generation stage. The bandgap reference voltage generation stage comprises a device with a PN-junction, a current source feeding a first current during a first period of time and a second higher current during a second period of time through the PN-junction. The bandgap reference voltage is generated from a combination of a first voltage drop across the PN-junction during the first period of time and a second voltage drop across the PN-junction during the second period of time. This bandgap reference voltage is formed using switched capacitors.

Electronic device and method providing a voltage reference

An electronic device generates a current with a predetermined temperature coefficient. The circuit comprises a temperature coefficient (TC) component receiving a bias current, a differential amplifier providing a buffered output voltage based on the voltage across the TC component and a resistor receiving an TC current based on the differential amplifier output voltage. The differential amplifier has a predetermined input related offset which decreases the voltage drop across the resistor. The temperature coefficient component could have either a negative temperature component (NTC) or a positive temperature component (PTC).

Bias current generator

An electronic device comprising a first supply voltage domain, a second supply voltage domain and a low drop output voltage regulator (LDO) coupled to receive a supply voltage of the first supply voltage domain and to provide a supply voltage of the second supply voltage domain and the LDO being configured to be switched into a first state for providing and maintaining the supply voltage of the second supply voltage domain and into a second state for providing a high impedance output to the second supply voltage domain. The electronic device includes a comparator coupled to monitor the first supply voltage level at a first supply voltage node and to switch the LDO from the first state to the second state.

Electronic device for monitoring a supply voltage

An integrated circuit provides a power on reset signal with respect to a supply voltage level supplying the electronic device. The integrated circuit comprises a bias current generating stage having a first current mirror and an output stage having first, second and third series connected MOS transistors. A connection between the second MOS transistor and the third MOS transistor forms a POR output node. A gate of the second MOS transistor and a gate of the third MOS transistor are coupled to each other and to the first current mirror. This allows a current through the third MOS transistor when the supply voltage is higher than a first MOS transistor threshold and a current through the second MOS transistor only when the supply voltage is greater than or equal to the sum of the first MOS transistor threshold and a second MOS transistor threshold voltage.

Power-on reset circuit

The present invention relates to controlling the refresh rate of the reference voltage on a sampling capacitor (C). A comparator (COMP) compares the voltage on a first capacitor (C) with the voltage on a second capacitor (C). These capacitors have the capacitance of the sampling capacitor (C). Upon each refresh the first capacitor (C) samples a first voltage (V) and the second capacitor samples a lower second voltage (V). The first capacitor (C) is discharged at a first current Ivia a first leakage current source (D). The second capacitor (C) is discharged at a second current Ivia a second leakage current source (D). The comparator (COMP) triggers a refresh when the voltages equal. The first current Iis preferably an integer N times the second current I.

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Unterschleissheim, Germany

Johannes Gerber