Infineon Technologies Ag

Infineon Technologies Austria Ag

Infineon Technologies Dresden Gmbh & Co. Kg

Johannes Georg Laven

Hans-Joachim Schulze

Roman Baburske

Christian Jaeger

Alexander Philippou

Werner Schustereder

Matteo Dainese

Antonio Vellei

Anton Mauder

Frank Dieter Pfirsch

Thomas Basler

Erich Griebl

Moriz Jelinek

Peter Lechner

Francisco Javier Santos Rodriguez

Maria Cotorogea

Markus Beninger-Bina

Christian Philipp Sandow

Philip Christoph Brandt

Joachim Mahler

Franz-Josef Niedernostheide

Caspar Leendertz

Ingo Dirnstorfer

Franz Hirler

Hans Weber

Markus Bina

Peter Irsigler

Guenther Ruhl

Holger Schulze

Helmut Oefner

Daniel Tutuc

Andreas Voerckel

Maximilian Treiber

Helmut Maeckel

Roland Rupp

Franz Josef Niedernostheide

Roman Knoefler

Elmar Falck

Manfred Pfaffenlehner

Daniel Schloegl

Andre Rainer Stegner

Michael Stadtmueller

Hans-Peter Felsl

Andreas Haertl

Andreas Haghofer

Heiko Rettinger

Max Christian Seifert

Christian Kegler

Dieter Fuchs

Haybat Itani

Markus Zundel

Reinhold Bayerer

Helmut Strack

Wolfgang Roesner

Maximilian Roesch

Stephan Voss

Alexander Breymesser

Daniel Domes

Peter Kanschat

Rudolf Berger

Anton Prueckl

Frank Wolter

Robert Strenz

Holger Huesken

Thomas Gutt

Uwe Jansen

Christian Robert Mueller

Martin Stiftinger

Daniel Pedone

Alexander Susiti

Naveen Goud Ganagona

Andre Schwagmann

Michael Brugger

Patrick Schwarz

Shuhai Liu

Stefan Buschhorn

Martin Faccinelli

A power semiconductor device having a barrier region is provided. A power unit cell of the power semiconductor device has at least two trenches that may both extend into the barrier region. The at least two trenches may both have a respective trench electrode coupled to a control terminal of the power semiconductor device. For example, the trench electrodes are structured to reduce the total gate charge of the power semiconductor device. The barrier region may be p-doped and vertically confined, i.e., in and against the extension direction, by the drift region. The barrier region can be electrically floating.

Power semiconductor device with dV/dt controllability and low gate charge

A power semiconductor device includes: a drift region; a plurality of IGBT cells each having a plurality of trenches extending into the drift region along a vertical direction and laterally confining at least one active mesa which includes an upper section of the drift region; and an electrically floating barrier region of an opposite conductivity type as the drift region and spatially confined, in and against the vertical direction, by the drift region. A total volume of all active mesas is divided into first and second shares, the first share not laterally overlapping with the barrier region and the second share laterally overlapping with the barrier region. The first share carries the load current at least within a range of 0% to 100% of a nominal load current. The second share carries the load current if the load current exceeds at least 0.5% of the nominal load current.

Power semiconductor device having a barrier region

A power semiconductor device includes: first and second trenches extending from a surface of a semiconductor body along a vertical direction and laterally confining a mesa region along a first lateral direction; source and body regions in the mesa region electrically connected to a first load terminal; and a first insulation layer having a plurality of insulation blocks, two of which laterally confine a contact hole. The first load terminal extends into the contact hole to contact the source and body regions at the mesa region surface. A first insulation block laterally overlaps with the first trench. A second insulation block laterally overlaps with the second trench. The first insulation block has a first lateral concentration profile of a first implantation material of the source region along the first lateral direction that is different from a corresponding second lateral concentration profile for the second insulation block.

Power semiconductor device with p-contact and doped insulation blocks defining contact holes

A power semiconductor device includes a semiconductor body coupled to first and second load terminals. The body includes: at least a diode structure configured to conduct a load current between the terminals and including an anode port electrically connected to the first load terminal and a cathode port electrically connected to the second load terminal; and drift and field stop regions of the same conductivity type. The cathode port includes first port sections and second port sections with dopants of the opposite conductivity type. A transition between each of the second port sections and the field stop region forms a respective pn-junction that extends along a first lateral direction. A lateral separation distance between immediately adjacent ones of second port sections in a second group is smaller than in a first group.

Diode structure of a power semiconductor device

A method for fabricating a semiconductor device includes: forming a trench in a first major surface of a semiconductor body having a first conductivity type; forming a gate in the trench; forming a body region of a second conductivity type in the semiconductor body; implanting a second dopant species into a first region of the body region and a first dopant species into a second region of the body region, the first dopant species providing the first conductivity type, the second dopant species being different from the first dopant species and reducing the diffusion of the first dopant species in the semiconductor body; and thermally annealing the semiconductor body to form a source region that includes the first and second dopant species, and to produce a pn-junction between the source and body regions at a depth dfrom the first major surface, wherein 50 nm&#x3c;d&#x3c;300 nm.

Method for manufacturing a semiconductor device

A semiconductor device includes: a semiconductor region having charge carriers of a first conductivity type; a transistor cell in the semiconductor region; a semiconductor channel region in the transistor cell and having a first doping concentration of charge carriers of a second conductivity type, wherein a transition between the semiconductor channel region and the semiconductor region forms a first pn-junction; a semiconductor auxiliary region in the semiconductor region and having a second doping concentration of charge carriers of the second conductivity type. A transition between the semiconductor auxiliary region and semiconductor region forms a second pn-junction positioned deeper in the semiconductor region as compared to the first pn-junction. The semiconductor auxiliary region is positioned closest to the semiconductor channel region as compared to any other semiconductor region having charge carriers of the second conductivity type and that forms a further pn-junction with the semiconductor region.

Semiconductor device having a semiconductor channel region and a semiconductor auxiliary region

An power semiconductor device having a barrier region is provided. A power unit cell of the power semiconductor device has at least two trenches that may both extend into the barrier region. The at least two trenches may both have a respective trench electrode coupled to a control terminal of the power semiconductor device. For example, the trench electrodes are structured to reduce the total gate charge of the power semiconductor device. The barrier region may be p-doped and vertically confined, i.e., in and against the extension direction, by the drift region. The barrier region can be electrically floating.

A power semiconductor switch includes an active cell region with a drift region, an edge termination region, and IGBT cells within the active cell region. Each IGBT cell includes trenches that extend into the drift region and laterally confine mesas. At least one control trench has a control electrode for controlling the load current. At least one dummy trench has a dummy electrode electrically coupled to the control electrode. At least one further trench has a further trench electrode. At least one active mesa is electrically connected to a first load terminal within the active cell region. Each control trench is arranged adjacent to no more than one active mesa. At least one inactive mesa is adjacent to the dummy trench. A cross-trench structure merges each control trench, dummy trench and further trench to each other. The cross-trench structure overlaps at least partially along a vertical direction with the trenches.

Power semiconductor switch having a cross-trench structure

A method of processing a power semiconductor device includes: providing a semiconductor body with a drift region of a first conductivity type; forming a plurality of trenches extending into the semiconductor body along a vertical direction and arranged adjacent to each other along a first lateral direction; providing a mask arrangement at the semiconductor body, the mask arrangement having a lateral structure according to which some of the trenches are exposed and at least one of the trenches is covered by the mask arrangement along the first lateral direction; forming, below bottoms of the exposed trenches, a plurality of doping regions of a second conductivity type complementary to the first conductivity type; removing the mask arrangement; and extending the plurality of doping regions in parallel to the first lateral direction such that the plurality of doping regions overlap and form a barrier region of the second conductivity type adjacent to the bottoms of the exposed trenches.

Method of processing a power semiconductor device

A power semiconductor device includes an active cell region with a drift region of a first conductivity type, a plurality of IGBT cells arranged within the active cell region, each of the IGBT cells includes at least one trench that extends into the drift, an edge termination region surrounding the active cell region, a transition region arranged between the active cell region and the edge termination region, at least some of the IGBT cells are arranged within or extend into the transition region, a barrier region of a second conductivity type, the barrier region is arranged within the active cell region and in contact with at least some of the trenches of the IGBT cells and does not extend into the transition region, and a first load terminal and a second load terminal, the power semiconductor device is configured to conduct a load current along a vertical direction between.

IGBT with dV/dt controllability

A power device includes: a diode section; a semiconductor body; a drift region extending into the diode section; trenches in the diode section and extending along a vertical direction into the semiconductor body, two adjacent trenches defining a respective mesa portion in the semiconductor body; a body region in the mesa portions; in the diode section, a barrier region between the body and drift regions and having a dopant concentration at least 100 times greater than an average dopant concentration of the drift region and a dopant dose greater than that of the body region. The barrier region has a lateral structure according to which at least 50% of the body region in the diode section is coupled to the drift region at least by the barrier region, and at least 5% of the body region in the diode section is coupled to the drift region without the barrier region.

Diode with structured barrier region

A semiconductor device is operable a forward current mode and a reverse current mode and comprises a semiconductor region, and a controllable charge carrier injector, and a gate. A method includes detecting, in the reverse current mode, if the present load current in the reversed direction does not exceed a threshold value, providing a gate signal such that the gate electrode causes the charge carrier injector to induce a first charge carrier density within the semiconductor region so as to conduct a nominal load current in the reverse direction; if the present load current in the reverse direction does exceed the threshold value, operating the semiconductor device in an overload state by providing the gate signal with a voltage that causes the semiconductor region to conduct an overload current in the reverse direction, wherein the second charge carrier density is higher than the first charge carrier density.

Semiconductor device having overload current carrying capability

An RC IGBT with an n-barrier region in a transition section between a diode section and an IGBT section is presented.

RC IGBT with an IGBT section and a diode section

A power inverter includes a bridge circuit including a first half-bridge and a second half-bridge, each half-bridge including a high-side device and a low-side device, and a gate driver circuit connected with each gate of the high-side device and low-side power device of the first and second half-bridges and operable to provide each gate with a respective voltage to control operation of the respective power device. The gate driver is operable to provide a first voltage which is higher than a first threshold voltage of the respective power device, and a second voltage which is higher than a surge threshold of the respective power device. The surge threshold is higher than the first threshold and defines the onset of a surge current operation area of the respective power device at which the power device becomes conducts a surge current that is larger than the rated current of the device.

Semiconductor device with surge current protection

Forming a semiconductor arrangement includes providing a first semiconductor layer having a first surface, forming a first plurality of trenches in the first surface of the first semiconductor layer, each of the trenches in the first plurality having first and second sidewalls that extend from the first surface to a bottom of the respective trench, implanting first type dopant atoms into the first and second sidewalls of each of the trenches in the first plurality, implanting second type dopant atoms into the first and second sidewalls of each of the trenches in the first plurality, and annealing the semiconductor arrangement to simultaneously activate the first type dopant atoms and the second type dopant atoms.

Method for producing a superjunction device

Growing community of inventors

Taufkirchen, Germany

Johannes Georg Laven