International Business Machines Corporation

Johannes G Beha

Gary W Rubloff

Russell W Dreyfus

Rolf Clauberg

Armin U Blacha

Allan Mark Hartstein

Jeffrey Alan Kash

Hugo K Seitz

Peter Vettiger

Ronald Pete Luijten

Wolfgang D Pohl

Antonius Paulus Engbersen

Wolfgang Emil Denzel

Hamid Ahmadi

Heinz Jaeckel

Erich Port

Charles Allen Murphy

Rolf B Moeller

In a switching system interconnecting transmission links (21-i, 23-i) on which circuit switched (CS) and packet switched (PS) information is transferred, a switch fabric (11) is provided which interconnects a plurality of input ports (15-i) to a plurality of output ports (19-i). The information arriving on incoming links is converted in switch adapters (13-i) to uniform minipackets, each having a routing address designating the required output port. The switch fabric consists of parallel equal switching slices, e.g. binary routing trees (71), which transfer in a non-blocking manner each minipacket from its input port to one output port in response to the routing address. Collecting means (73, 75) are provided at each output port for accepting the minipackets arriving from the different input ports.

High-speed modular switching apparatus for circuit and packet switched

For testing the integrity of conducting lines on or in a substrate, the following steps are executed: (I) Selected pads are irradiated by a focused optical beam so that they are positively charged due to photon-assisted tunneling of electrons from those pads. The charges propagate through existing conductors so that all selected pads and all pads connected to them assume a specific voltage. (II) The whole surface is irradiated by a flooding optical beam. Photon-assisted tunneling of electrons will now occur from those pads which were not charged previously. (III) The tunneling electrons excite an electroluminescent layer whose illumination reveals the spatial distribution of uncharged pads. This method is performed in air under atmospheric conditions and allows completely contactless testing of circuitry to detect line interruptions as well as shortcuts between separate lines. It is suited for surface lines, buried lines and for via connections.

Method for contactless testing of conducting paths in a substrate using

For observing material structures and/or dynamic processes at surfaces, the known scanning tunneling microscope (STM) is combined with a photoexcitation process leading to photon-assisted tunneling. Thereby, the very fine spatial resolution of the STM is combined with the picosecond or even femtosecond time resolution of laser pulses. The tunnel tip of a scanning tunneling microscope is positioned at tunnel distance with respect to the surface of the sample to be investigated, with an appropriate potential applied across the gap between the tunnel tip and the sample. The tunneling current is gated by means of at least one pulsed laser beam directed at the tuneling region and/or at the tunnel tip.

Method for investigating surfaces at nanometer and picosecond resolution

Contactless probing of an integrated circuit is carried out by flooding the surface of the integrated circuit with pulsed ultraviolet laser light, causing photoelectron emission as a function of the potentials at micropoints on the integrated circuit, converting this two-dimensional electron pattern into a corresponding relatively long duration pattern of luminescence by a luminescent target, and reviewing the result by video/computer scanning. Separate embodiments allow testing either in vacuum or in air, with or without insulating passivation layers present on the chip. The result is a contactless oscilloscope which monitors instantaneous voltages (logic states and AC switching waveforms) for a full two-demsnsional array of micropoints simultaneously. A chip with test points and appropriate windows for laser activation and luminescent targeting can be specially designed for optimal testing.

Full chip integrated circuit tester

A method for contactlessly testing for opens and shorts in conducting paths within or on a nonconducting substrate. There are a plurality of conducting pads on the surface of the substrate. Charges are contactlessly generated, e.g., by an optical beam, in at least one selected pad inducing a voltage thereon and on pads electrically connected therewith through one of the conducting paths. A two dimensional electron flux is contactlessly caused to be emitted from the selected pad and at least one other pad of the plurality of pads, e.g., by an optical beam. The flux emitted from the pads depends on the voltage on each pad. The flux is detected to distinguish pads in electrical connection.

Method for contactless testing for electrical opens and short circuits

Covering metal test pads of a passivated integrated circuit process intermediate wafer or completed integrated circuit chip-to-test, with a thin conductive overlayer, and then accessing the test pads through the passivation layer and conductive overlayer, by a pulsed laser to provide voltage-modulated photon-assisted tunneling through the insulation layer, to the conductive overlayer as an electron current, and detecting the resulting electron current, provides a nondestructive test of integrated circuits. The passivation, normally present to protect the integrated circuit, also lowers the threshold for photoelectron emission. The conductive overlayer acts as a photoelectron collector for the detector. A chip-to-test which is properly designed for photon assisted tunneling testing has test sites accessible to laser photons even though passivated. Such a chip-to-test may be nondestructively tested in air at one or several stages of its processing, without the sacrifices of mechanical probing or of bringing test sites out to output pads. The conductive overlayer may be removed after tests have been completed. Integrated circuit process intermediate chips may be specially designed for testability, with test sites grouped for easy access through windows left uncovered by subsequent layers.

Photon assisted tunneling testing of passivated integrated circuits

Testing of integrated circuit process intermediates, such as wafers, dise or chips in various stages of production (test chips) is facilitated by a nonintrusive, noncontact dynamic testing technique, using a pulsed laser, with laser light modification to increase photon energy through conversion to shorter wavelength. The high energy laser light excites electron emissions to pass to the detection system as a composite function of applied light energy and of dynamic operation of the circuit; detecting those emissions by an adjacent detector requires no ohmic contacts or special circuitry on the integrated circuit chip or wafer. Photoelectron energy emitted from a test pad on the test chip is detected as a composite function of the instantaneous input voltage as processed on the test chip, in dynamic operation including improper operation due to fault. The pulse from the laser, as modified through light modification, the parameters of detection of bias voltages, and the distances involved in chip-grid-detector juxtaposition, provides emissions for detection of circuit voltages occurring on the test chip under dynamic conditions simulating actual or stressed operation, with high time resolution of the voltages and their changes on the circuit.

Noncontact dynamic tester for integrated circuits

Contactless probing of an integrating circuit is carried out by flooding the surface of the integrated circuit with pulsed ultraviolet laser light, causing photoelectron emission as a function of the potentials at micropoints on the integrated circuit, converting this two-dimensional electron pattern into a corresponding relatively long duration pattern of luminescence by a luminescent target, and reviewing the result by video/computer scanning. Separate embodiments allow testing either in vacuum or in air, with or without insulating passivation layers present on the chip. The result is a contactless oscilloscope which monitors instantaneous voltage (logic states and AC switching waveforms) for a full two-dimensional array of micropoints simultaneously. A chip with test points and appropriate windows for laser activation and luminescent targeting can be specially designed for optimal testing.

Simultaneous noncontact testing of voltages across a full line of test sites on an integrated circuit chip-to-test is achieved with high time resolution using photoelectron emission induced by a pulsed laser focussed to a line on the chip-to-test, together with high speed electrostatic deflection perpendicular to the line focus. Photoelectrons produced by the line focus of pulsed laser light are imaged to a line on an array detector, the measured photoelectron intensities at array points along this line representing voltages at corresponding points along the line illuminated by the laser focus. High speed electrostatic deflection applied during the laser pulse, perpendicular to the direction of the line focus, disperses the line image (column) on the array detector across a sequence of sites at right angles (rows), thereby revealing the time-dependence of voltages in the column of test sites with high time resolution (in the picosecond range).

Noncontact full-line dynamic AC tester for integrated circuits

Planar junction Josephson interferometer in which the junctions (24) are 'buried' underneath the interferometer bridge (27) connecting the junction counter-electrodes (25). The insulation (26) that separates the common base electrode (22) from the bridge (27) is extended between the bridge and the upper surfaces of the counter-electrodes. This design permits, without decreasing the interferometer loop inductance, a reduction of the interferometer area and thus results in a higher packaging density in logic or memory applications. The buried junction concept can be applied in symmetric or asymmetric interferometer designs with virtually any number of junctions, any type of input current control or current feeding scheme. The interferometer can be produced using conventional evaporation, photo-resist, and etch processes based on optical lithography. Further area reduction is achieved in applying e-beam or x-ray technology.

Growing community of inventors

Wadenswil, Switzerland

Johannes G Beha