Austriamicrosystems Ag

Ams Ag

Johannes Fellner

Gregor Schatzberger

Peter Bösmüller

Michael Böhm

The invention relates to an input circuit arrangement (), which is designed for operation either in a first or a second operating mode (A, B) and comprises a connection () for supplying a connection signal (SWI) and a detection circuit (). The detection circuit () is coupled on the input side to the connection () and is designed to put the input circuit arrangement () into an operating mode from a group comprising the first and second operating modes (A, B) depending on the steepness of a change of the connection signal (SWI).

Input circuit arrangement, output circuit arrangement, and system having an input circuit arrangement and an output circuit arrangement

A circuit arrangement including a fuse comprises a fuse path (SP) which is coupled to a control input (SE) and comprises the fuse (RS) and a first charge reservoir (C) serially connected thereto for providing a first charge state (L), a reference path (RP) which is coupled to the control input (SE) and comprises a comparison element (RV) and a second charge reservoir (C) serially connected thereto for providing a second charge state (L), and an evaluation unit (AE) comprising a first input (E) connected to the fuse path (SP) in a switchable manner, a second input (E) connected to the reference path (RP) in a switchable manner, and a data output (DA) for providing a condition of the fuse (RS) depending on a difference between the first and second charge states (L, L). Further, a method for determining the condition of a fuse is provided.

Circuit arrangement comprising a fuse and a method for determining a condition of a fuse

A circuit arrangement comprises a memory cell array () with at least one memory circuit (). The memory circuit () comprises one non-volatile memory cell () inserted in a first current path () between a supply voltage terminal () and a reference potential terminal (), and a volatile memory cell () inserted in a second current path () between the supply voltage terminal () and the reference potential terminal (). The volatile memory cell () is coupled to the non-volatile memory cell () for reading the non-volatile memory cell ().

Circuit arrangement comprising a memory cell field and method for operation thereof

A circuit arrangement for operating voltage detection has a detection block () and a control block (). Detection block () has a first transistor (P) that is connected between a first supply voltage terminal (VDD) and a first node (K) and has a first control terminal (S), a first resistor element (R) that is connected between first node (K) and second supply voltage terminal (VSS), a second transistor (P) that is connected between first supply voltage terminal (VDD) and a second node (K) and has a second control terminal (S), a second resistor element (R) that is connected between second node (K) and second supply voltage terminal (VSS), a first switch (N) that connects first node (K) to second control terminal (S), and a third resistor element (R) that is connected between second control terminal (S) and first supply voltage terminal (VDD). Control block (K) is set up to derive a first switching signal as a function of a voltage at second node (K), as well as a second switching signal by inverting the first switching signal. The first switching signal is supplied to first switch (N), and the second switching signal to first control terminal (S).

Circuit arrangement for operating voltage detection

In one embodiment, a readout circuit for rewritable memories comprises a control logic unit with an input for supplying a start signal and with several outputs for providing a respective control signal as a function of start signal, a first terminal for switchable connection to a first memory cell by means of a first switch, and a second terminal for switchable connection by means of a second switch to a second memory cell, and a readout unit coupled to the control logic unit, as well as to the first and second terminals, with an output for providing an output signal as a function of a state of the first and/or the second memory cell and as a function of the control signals, wherein the readout circuit is designed for self-terminating operation in a reading mode and in a test mode. A readout method for rewritable memories is additionally provided.

Readout circuit for rewritable memories and readout method for same

The circuit arrangement comprises a symmetrically constructed comparator (), a non-volatile memory cell () and a reference element (). The comparator () exhibits a latching function, and is connected in a differential current path that joins the power supply terminal () to a reference potential terminal (). The non-volatile memory cell () is connected in a first branch () of the differential current path, and the reference element () is connected in a second branch () of the differential current path.

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Pirka, Austria

Johannes Fellner