Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Johannes Christian Thiele

Olivier Bichler

Vincent Lorrain

David Briand

Marc Duranton

An electronic calculator comprises a plurality of electronic calculation blocks, each of which is configured to implement one or more respective processing layers of an artificial neural network. The calculation blocks are of at least two different types among: a first type with fixed topology, fixed operation, and fixed parameters, a second type with fixed topology, fixed operation, and modifiable parameters, and a third type with modifiable topology, modifiable operation, and modifiable parameters. For each processing layer implemented by the respective calculation block, the topology is a connection topology for each artificial neuron, the operation is a type of processing to be performed for each artificial neuron, and the parameters include values determined via training of the neural network.

Electronic calculator for the implementation of an artificial neural network, with calculation blocks of several types

A new implementation is provided for an error back-propagation algorithm that is suited to the hardware constraints of a device implementing a spiking neural network. The invention notably uses binary or ternary encoding of the errors calculated in the back-propagation phase to adapt its implementation to the constraints of the network, and thus to avoid having to use floating-point number multiplication operators. More generally, the invention proposes a global adaptation of the back-propagation algorithm to the specific constraints of a spiking neural network. In particular, the invention makes it possible to use the same propagation infrastructure to propagate the data and to back-propagate the errors in the training phase. The invention proposes a generic implementation of a spiking neuron that is suitable for implementing any type of spiking neural network, in particular convolutional networks.

Backpropagation of errors in pulsed form in a pulsed neural network

A computer-implemented method for coding a digital signal intended to be processed by a digital computing system includes the steps of: receiving a sample of the digital signal quantized on a number Nof bits, decomposing the sample into a plurality of binary words of parameterizable bit size N, coding the sample through a plurality of pairs of values, each pair comprising one of the binary words and an address corresponding to the position of the binary word in the sample, transmitting the pairs of values to an integration unit in order to carry out a MAC operation between the sample and a weighting coefficient.

Method and device for binary coding of signals in order to implement digital MAC operations with dynamic precision

A memory circuit for storing parsimonious data and intended to receive an input vector of size Iz, includes an encoder, a memory block comprising a first memory region and a second memory region divided into a number Iz of FIFO memories, each FIFO memory being associated with one component of the input vector, only non-zero data being saved in the FIFO memories, a decoder, the encoder being configured to generate an indicator of non-zero data for each component of the input vector, the memory circuit being configured to write the non-zero data of the input data vector to the respective FIFO memories and to write the indicator of non-zero data to the first memory region, the decoder being configured to read the outputs of the FIFO memories and the associated indicator in the first memory region.

Memory circuit for storing parsimonious data

A method for unsupervised learning of a multilevel hierarchical network of artificial neurons wherein each neuron is interconnected with artificial synapses to neurons of a lower hierarchical level and to neurons of an upper hierarchical level. The method includes at a neuron the steps of integrating inference spikes from the interconnected neurons of the lower hierarchical level both in a first and a second accumulators using the same synaptic weights; when the first accumulator reaches a first threshold, generating a learning spike, resetting the first accumulator, triggering synaptic conductance modification in accordance with a spike-timing dependent plasticity rule and delivering the learning spike as an inhibitory signal to other neurons in the same hierarchical level; when the second accumulator reaches a second threshold, generating an inference spike, delivering the generated inference spike to the interconnected neurons of the upper hierarchical level, resetting the second accumulator and possibly delivering the inference spike as an inhibitory signal to other neurons in the same hierarchical level.

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Orsay, France

Johannes Christian Thiele