Synopsys, Inc.

Nxp B.v.

Johannes Boonstra

Rajendra Kumar

Marc Jeroen Geuzebroek

Pieter Van Der Wolf

Sundaravaradan Rangarajan

A system for executing tensor operations including: a programmable tensor processor; and a memory coupled to the programmable tensor processor, wherein the programmable tensor processor includes: one or more load AGU circuits to generate a first sequence of addresses and read input tensor operands from the memory based on the first sequence of addresses; a datapath circuit to perform the tensor operations on the input tensor operands based on receiving one or more instructions to determine output tensor operands, the one or more instructions being based on a loop iteration count and loop body micro-code instructions defining a loop body of a tensor program stored in the memory, the loop body micro-code instructions being executed in the programmable tensor processor; and a store AGU circuit configured to generate a second sequence of addresses and write the output tensor operands to the memory based on the second sequence of addresses.

Artificial intelligence (AI)/machine learning (ML) tensor processor

Memory arbiter with latency guarantees for multiple ports. A method of controlling access to an electronic memory includes measuring a latency value indicative of a time difference between origination of an access request from a port of a plurality of ports and a response from the electronic memory. The method also includes calculating a difference between the latency value for the port and a target value associated with the port. The method further includes calculating a running sum of differences for the port covering each of a plurality of access requests. Further, the method includes determining a delta of a priority value for the port based on the running sum of differences. Moreover, the method includes prioritizing the access by the plurality of ports according to associated priority values.

Memory arbiter with latency guarantees for multiple ports

A FIFO memory circuit is for interfacing between circuits with different clock domains. The circuit has a FIFO memory (), a write pointer circuit () clocked by the clock of a first clock domain and controlling the memory location to which data is written, and a read pointer circuit clocked by the clock of a second clock domain and controlling the memory location from which data is read. The read and write pointer circuits use gray coding. The memory circuit further comprises a duplicate write pointer circuit () which has its write pointer address incremented synchronously with the write pointer circuit (), and which has a starting write address selected such that the duplicate write pointer address lags behind the write pointer address circuit by a number of address locations corresponding to the size of the FIFO memory (). A comparator () compares the read pointer circuit address with the duplicate write pointer circuit address for determining a full status of the FIFO memory.

Growing community of inventors

Deurne, Netherlands

Johannes Boonstra