Koninklijke Philips Corporation N.v.

St-Ericsson Sa

Johannes Boonstra

Pieter Van Der Wolf

Josephus Theodorus Johannes Van Eijndhoven

Sandeep Agrawal

Sathya Jaganathan

A universal asynchronous receiver-transmitter module that includes a sampling controller that assigns a variable number of active edges in a clock signal to respective bits in a serial data signal. A serial data reception path derives a bit from the serial data signal on the basis of the variable number of active edges that the sampling controller has assigned to the bit.

Data processing apparatus

The disclosed data processing system comprises a memory means (SDRAM), a plurality of data processing means (IP) provided for accessing to said memory means (SDRAM), and a communication interface means coupled between said memory means (SDRAM) and said plurality of data processing means (IP), said communication interface means including a network of nodes (H, H, H), each node comprising at least one slave port (s) for receiving a memory access request from a data processing means (IP) or from a previous node and at least one master port (m) for issuing a memory access request to a next node or to said memory means (SDRAM) in accordance with the memory access request received at said slave port (s), wherein said at least one slave port (s) is connected to a master port (m) of a previous node or to one of said data processing means (IP) and said at least one master port (m) is connected to a slave port (s) of a next node or to said memory means (SDRAM).

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Eindhoven, Netherlands

Johannes Boonstra