St-ericsson Sa

Johannes Antonius Frambach

Paul Mateman

Leonardus Hesen

A duty-cycle correction circuit comprises a plurality of AC-coupled, independently-biased inverter stages connected in series. A periodic signal is applied to an input of the plurality of inverter stages. Each inverter stage comprises an inverter with a resistive element connected in feedback between its output and input nodes. Each inverter stage is AC-coupled to a prior stage via a capacitor. The AC-coupling allows the signal to pass between inverter stages, but DC-isolates each inverter stage from adjacent stages, allowing each stage to maintain an independent DC bias of the signal at that stage. By virtue of the feedback resistive element, each stage defines a transition point between high and low signal states. Due to non-zero rise and fall times of the periodic signal, the independent DC bias of each stage is operative to incrementally shift the transition point of the periodic signal at each stage towards a desired duty-cycle.

RF duty cycle correction circuit

An RF divider directly synthesizes a desired RF as a digital pattern that can be programmed and output at a VCO frequency. An exemplary RF divider comprises a pre-sequencer and a parallel-to-serial converter. The pre-sequencer successively outputs consecutive M-bit sections of a parallel word, where the parallel word comprises one or more copies of a frequency dividing bit pattern defining a frequency divisor. The parallel-to-serial converter performs a parallel-to-serial conversion on the M-bit sections of the parallel word based on the fixed radio frequency to generate an output signal having the desired radio frequency, where the output signal comprises a serial bit stream of the parallel word.

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Nijmegen, Netherlands

Johannes Antonius Frambach