Texas Instruments Corporation

Texas Instruments Incorporated Deutschland, Gmbh

Johann Zipperer

Horst Diewald

Peter Weber

Anton Brauchle

Christian Wiencke

Manish Goel

Srinivas Lingam

Seok-Jun Lee

Peter Wongeun Chung

Markus Koesler

Wolfgang Lutsch

Hans Martin Hilbig

Mark Jung

Volker Rzehak

Ronald Nerlich

Dietmar Walther

Erich Bayer

Leonardo William Estevez

Tobias Bernhard Fritz

Christophe Vaucourt

Jace Hunter Hall

Roger Neumair

A circuit includes a guard trigger circuit that includes a first input node adapted to be coupled to a first state signal, a second input node adapted to be coupled to a second state signal and an output node. The circuit also includes a reset synchronizer circuit that includes an input node coupled to the output node of the guard trigger circuit, a clock node adapted to be coupled to a clock signal and an output node. The circuit further includes a timeout circuit including an input node coupled to the output node of the reset synchronizer circuit, a clock node adapted to be coupled to the clock signal and an output node. The circuit still further includes a reset requestor circuit that includes a first input node coupled to the output node of the guard trigger circuit, a second node coupled to the output node of the timeout circuit.

Monitoring transitions of a circuit

A processor includes a plurality of execution units. At least one of the execution units is configured to determine, based on a first field of a first instruction, a number of additional instructions to execute in conjunction with the first instruction and prior to execution of the first instruction. The at least one of the execution units is further configured to determine, based on a second field of the first instruction, a subset of the additional instructions to execute atomically.

Processor that executes instruction that specifies instruction concatenation and atomicity

The invention relates to an apparatus and method for tracking energy consumption. An energy tracking system comprises at least one switching element, at least one inductor and a control block to keep the output voltage at a pre-selected level. The switching elements are configured to apply the source of energy to the inductors. The control block compares the output voltage of the energy tracking system to a reference value and controls the switching of the switched elements in order to transfer energy for the primary voltage into a secondary voltage at the output of the energy tracking system. The electronic device further comprises an ON-time and OFF-time generator and an accumulator wherein the control block is coupled to receive a signal from the ON-time and OFF-time generator and generates switching signals for the at least one switching element in the form of ON-time pulses with a constant width ON-time.

Tracking energy consumption using a buck-boosting technique

A method and apparatus for controlling pre-fetching in a processor. A processor includes an execution pipeline and an instruction pre-fetch unit. The execution pipeline is configured to execute instructions. The instruction pre-fetch unit is coupled to the execution pipeline. The instruction pre-fetch unit includes instruction storage to store pre-fetched instructions, and pre-fetch control logic. The pre-fetch control logic is configured to fetch instructions from memory and store the fetched instructions in the instruction storage. The pre-fetch control logic is also configured to provide instructions stored in the instruction storage to the execution pipeline for execution. The pre-fetch control logic is further configured set a maximum number of instruction words to be pre-fetched for execution subsequent to execution of an instruction currently being executed in the execution pipeline. The maximum number is based on a value contained in a pre-fetch threshold field of an instruction executed in the execution pipeline.

Processor with variable pre-fetch threshold

An electronic device and methods for providing high resolution ranging measurements are disclosed. The electronic device includes a pulse generator, a memory, an ADC, a timer, a comparator, a processing unit, connectors for coupling to a transceiver and instructions stored in the memory. The instructions, when performed by the processing unit, performs a method that determines an estimated time of arrival of a series of measurement pulses in the signal and turns on, prior to the estimated time of arrival, the ADC to capture the series of measurement pulses using a first resolution provided by sampling the signal at a rate equal to or greater than the Nyquist rate. The ADC remains on for a fixed time period sized to capture the series of measurement pulses.

Methods and electronic device for dynamic distance measurements

A transmission system includes a first device and a second device remote from the first device. The first device transmits electrical energy to a transmission line during a power provision phase, generates and transmits data symbols to the transmission line during a downstream transmission phase, and receives data symbols from the transmission line during an upstream transmission phase. The second device receives the energy from the transmission line during the power provision phase, receives the data symbols from the transmission line during the downstream transmission phase, and generates and transmits the data symbols to the transmission line during the upstream transmission phase, and the second device generates and transmits data symbols by shorting or disconnecting the transmission line. A method of transmitting electrical energy from the local device to the remote device, and communicating data symbols between the local and remote devices is also disclosed.

Baseband reflection modulation on power lines

A flow meter for determining the flow rate of a fluid through a conduit, including an upper body having an inlet chamber, an acoustic channel, an outlet chamber, a sound wave generator, and a sound wave receiver. The inlet chamber, acoustic channel, and outlet chamber are fluidly connected together and are oriented so as to create a symmetrical fluid pathway through the inlet chamber, the acoustic channel the outlet chamber. The sound wave generator and the sound wave receiver are aligned along a longitudinal axis of the acoustic channel and the sound wave generator is creates a sound wave that moves along the longitudinal axis of the acoustic channel as fluid flows through the acoustic chamber. The receiver detects that sound wave that has moved through the acoustic channel and such information is used to determine the flow rate of the fluid through the flow meter.

Hydraulic system for ultrasonic flow measurement using direct acoustic path approach

A processor includes a plurality of execution units. At least one of the execution units is configured to repeatedly execute a first instruction based on a first field of the first instruction indicating that the first instruction is to be iteratively executed.

Processor with instruction iteration

A semiconductor device comprising a processor having a pipelined architecture and a pipeline flattener and a method for operating a pipeline flattener in a semiconductor device are provided. The processor comprises a pipeline having a plurality of pipeline stages and a plurality of pipeline registers that are coupled between the pipeline stages. The pipeline flattener comprises a plurality of trigger registers for storing a trigger, wherein the trigger registers are coupled between the pipeline stages.

Pipeline flattener with conditional triggers

Methods and apparatus for a low energy accelerator processor architecture with short parallel instruction word. An integrated circuit includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory coupled to the system bus; and a low energy accelerator processor coupled to the system bus and configured to execute instruction words retrieved from a low energy accelerator code memory, the low energy accelerator processor having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, each of the execution units configured to perform operations responsive to op-codes decoded from the retrieved instruction words, wherein the width of the instruction words is equal to the data width N. Additional methods and apparatus are disclosed.

Low energy accelerator processor architecture with short parallel instruction word

A method of protecting software for embedded applications against unauthorized access is disclosed. Software to be protected is loaded into a protected memory area and access to the protected memory area is controlled by sentinel logic circuitry. The sentinel logic circuitry allows access to the protected memory area only either from within the protected memory area or from outside of the protected memory area but through a dedicated memory location within the protected memory area. The dedicated memory location then points to protected address locations within the protected memory area.

Method for protecting memory against unauthorized access

A processor includes a plurality of execution units. At least one of the execution units is configured to determine, based on a field of a first instruction, a number of additional instructions to execute in conjunction with the first instruction and prior to execution of the first instruction.

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Unterschleissheim, Germany

Johann Zipperer