Siemens Aktiengesellschaft

Infineon Technologies Ag

Infineon Technologies LLC

Johann Rieger

Johannes Stecker

Thomas Detzel

Werner Reczek

Hubert Maier

Thomas Von Der Ropp

Hartmud Terletzki

Xaver Guggenmos

Wolfgang Nikutta

Stefan Lipp

Johann Stecker

Hans Peter Zeindl

Ioannis Chrysostomides

Methods for forming an integrated semiconductor circuit arrangement are disclosed. In one embodiment, a semiconductor circuit with a first semiconductor circuit region and with a second semiconductor circuit region is formed in each case in a semiconductor material region. A first metallization layer is applied to the structure thus obtained. A protective material region is then formed. A second metallization layer is subsequently applied, which is then also patterned. Afterward, the first metallization layer together with the protective material region is then patterned.

Method for forming an integrated semiconductor circuit arrangement

A method for checking a semiconductor memory device integrated on a semiconductor chip includes providing the semiconductor memory device with a plurality of memory cells each being disposed on a semiconductor substrate for one binary information value, data lines for reading out and writing in information values, gate transistors being associated with the memory cells for selectively clearing a data path between a given memory cell and a data line, selection lines for purposefully triggering the gate transistors, and at least one in-chip reference voltage being adjusted to a predetermined normal value when the semiconductor memory device is functioning as intended. The method for checking the semiconductor memory device integrated on a semiconductor chip is carried out by at least intermittently varying the at least one in-chip reference voltage, and detecting and weighting the information values read out at the at least intermittently varied reference voltage.

Method for checking a semiconductor memory device

A DRAM with an address space divided into blocks, in which storage cells of individual blocks can be activated by a row address signal (RAS) furnished by a controller. Each individual block can then be activated by an independent activation signal derived from the row address signal. The activation signals for different blocks are supplied to the different blocks in succession with a partial time overlap, so that the obtained data rate is increased relative to activation of only one block, owing to partial time activation of at least two different blocks.

DRAM including an address space divided into individual blocks having

A bootstrap circuit includes a transfer transistor and a driver transistor of the same channel type each having two channel terminals and a gate. A first signal terminal receives a first signal and a second signal terminal receives a second signal. One of the channel terminals of the transfer transistor is connected to the gate of the driver transistor. The other of the channel terminals of the transfer transistor is connected to the first signal terminal. One of the channel terminals of the driver transistor is connected to the second signal terminal. The other of the channel terminals of the driver transistor forms an output of the bootstrap circuit. A configuration generates a third signal and has an output connected to the gate of the transfer transistor. The second signal has an edge extending from a first level to a second level and beginning at a bootstrap time. The first signal has a precharging level between the first level and the second level of the second signal occurring no later than another time being at the latest equal to the bootstrap time. After the other time, the third signal has a first level being equal to or located on the other side of the level of the first signal as seen from the second level of the second signal. Before the other time, the third signal has a second level being on the same side of the precharging level of the first signal as seen from the second level of the second signal.

Bootstrap circuit and integrated memory circuit having the bootstrap

An evaluation and amplifier circuit of the type of a keyed flipflop including at least two first transistors of a given channel type connected in series to each other disposed between first and second signal lines, has a connection from the gates of the first transistors to a respective one of the second and first signal lines. The first two transistors respectively form a first node common to the first two transistors for receiving a first control signal. A series circuit has at least two second transistors of the same channel type as the first transistors being connected in parallel to the first transistors, The gates of the first transistors are further connected with a respective one of the second and first signal lines. Furthermore, the amplifier circuit includes the feature that the second transistors form a second node common to the second transistors for receiving a second control signal, and a differential signal appearing on the signal lines is evaluated and amplified by the second transistors after the first transistors have received the differential signal.

Evaluation and amplifier circuit

Integrated semiconductor memory device having a semiconductor substrate with a redundant circuit arrangement formed thereon for replacing a defective memory cell of the integrated semiconductor memory device by selecting a redundant memory cell likewise disposed on the semiconductor substrate, the memory cells of the integrated semiconductor memory device being constructed and addressable in blocks; the redundant memory cells being combined into a redundant memory cell field addressable as a unit by the redundant circuit arrangement; and the redundant circuit arrangement having a redundant selection circuit for selecting a redundant memory cell from the redundant memory cell field to replace a defective memory cell from any of the memory cell blocks, includes a redundance control circuit forming part of the redundant circuit arrangement and enabling, as a function of a programmed redundant selection signal, one of the data content of a normal memory cell and the data content of a redundant memory cell suitably substituted in the event of a defect in the normal memory cell of the redundant memory cell field, the redundance control circuit being connected downstream from read amplifier circuits for reading out data from the normal memory cells and from read amplifier circuits for reading out redundant data from the redundant memory cells.

Integrated semiconductor memory device

Integrated semiconductor memory having normal memory cells arranged at intersections of word lines and bit lines, decoders for selecting a word line as a function of applicable word line address signals decoders for selecting a bit line as a function of applicable bit line address signals, external reading and evaluator circuits associated with the bit lines of the normal memory cells and connected on an output side thereof with data lines whereat data content is to be output, and redundant memory cells, additionally, by at least one programmable redundant decoder for replacing a defective memory cell, includes external redundant reading and evaluator circuits triggerable by the at least one programmable redundant decoder and associated with the redundant memory cells, the external redundant reading and evaluator circuits being connectible on the input side with the redundant memory cells and on the output side with the data lines, and a redundant control circuit associated with each of the external redundant reading and evaluator circuits, the redundant control circuit being connected to and between the respective associated external redundant reading and evaluator circuit and the data lines and, as a function of a redundant selection signal which is output by the redundant decoder, enabling the data content of a redundant memory cell present at the output of an external redundant reading and evaluator circuit to be transmitted to a selected data line.

Integrated seminconductor memory

A semiconductor component includes a semiconductor body having a terminal pad, a semiconductor function element, and an electrically conductive connecting line connecting the terminal pad to the semiconductor function element. A protective element for protecting against electrostatic discharge is connected between the terminal pad and the semiconductor function element. A first supply line for a first supply potential is connected to the semiconductor function element. A second supply line for the first supply potential is connected to the protective element and is electrically conductively connected to the first supply line. A clamp element is connected to the connecting line and to the first supply line, for limiting a voltage applied to the clamp element to a clamp value.

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Zell, Germany

Johann Rieger