U.S. Philips Corporation

Johann E Kruger

Ulrich R Killat

Wolfgang E Jasmer

Bernhard Hill

Rudiger Pepperl

Olaf H Dossel

Gert Rabe

Wolfgang Hoppe

Rolf U Kobs

Kai-Michael Ludeke

Wilfried Edeler

Bernd R David

Wolfang E Jasmer

A miniaturized SQUID module (10), notably for multi-channel magnetometers, for measurement of varying magnetic fields in a field strength range below 10.sup.-10 T, includes superconducting and shielded connections between a SQUID chip (19) and a gradiometer (12). The module can be mounted in the lower part of a cryostat and enables a large number of measurement points per unit of surface area. The SQUID chip (19) is arranged on a fully shielded supporting plate (18) which has a width of only a few millimeters and which is provided with electronic circuitry (23), the SQUID chip (19) being connected in a superconducting manner, at least by soldering, to the wires (11) of the gradiometer (12) via a superconducting, solderable and bondable intermediate support (27).

Miniaturized squid module having an intermediate super conducting

The feedback current for the flux-locked-loop of a DC-SQUID is conductively supplied directly to the input circuit of the SQUID rather than to a separate feedback or modulation coil that is inductively coupled to the SQUID, thereby eliminating the feedback or modulation coil and simplifying construction of an integrated SQUID module.

Squid magnetometer in which feedback current for a squid

In the framework of the development of future, integrated wideband networks, specifically the arrangement of the switching networks and switching network controls is of particular importance. In a switching network arranged in accordance with a space-division multiplex switching network each switching point comprises a comparator, comparing the addresses of the trunk lines arranged column-by-column to the routing information. When there is multiple correspondence in a column a decision circuit assigned to the trunk line decides the order in which the switching points are to switch. In addition, an input buffer is connected to each supply line, in which buffer the blocks are temporatily stored until they can reach one of the trunk lines. To avoid the occurrence of bottle-necks in the performance of the switching network an input buffer is assigned to each switching point or the switching network is arranged column-by-column and built up of units of equal structure.

Switching network and switching network control for a transmission system

In broadband space-division switching networks a multi-layer p.c. board is used for wiring the switching matrices of adjacent switching stages. In case of a plurality of links between the switching matrices a corresponding number of layers of the p.c. board can be provided. The connection of the individual layers of the p.c. board requires much expenditure in point of manufacturing engineering. This expenditure can be reduced in a surprisingly simple manner, when a canonical linkage in a p.c. board is introduced such, that link sections of the switching matrix are fanned out into groups onto a layer of the p.c. board and combined again. By dividing the links into sections, requirements as regards equal line length, reduction of space required and replacement in case of defects can be met in a simple manner.

Broadband space-division switching network with linkage in a printed

The invention relates to a switching network for a communication system, comprising m/1 stages and in which cells are transmitted in accordance with a time-division multiple access method and the switching is effected on the basis of the routing information contained in the header. The arriving cells are temporarily stored in a buffer until a free frame is available. The queues built up in the buffers of the m/1 stages are to be processed in the most fair manner. For this purpose it is proposed to assign a memory to each m/1 stage of each auxiliary line (Zl . . . Zm), to which memory are applied the results of the comparisons between routing information and address of the trunk line (A) and to determine for the decision circuits the order in which the cells stored in the buffers (B) are read out.

Packet switching network for a communication system

The invention relates to a switching network for a switching system in which cells are transmitted in accordance with a time division multiplex method and the through-connection is effected by means of the routing information contained in the header of the cells. The blocks arriving at the switching node are temporarily stored in a queuing buffer until a free frame is available. A switching network should be configured in such a manner that the number of buffer spaces can become as small as possible and buffer spaces only need to be provided for data which are to be forwarded via the associated serving trunk. To this end, it is proposed to allocate a comparator to each offering trunk, the comparator comparing the address of the serving trunk with the routing information and the cells supplied in the offering trunk only being entered into the buffer store associated with the serving trunk in the case of a correspondence between routing information and stored address of this serving trunk.

Switching network for a switching system

In a switching system, more specifically a packet switching system, the flow control of the packets can be established by way of a datagram or by implementing the method of the virtual connection. For the optimization of the flow control the selected structure of the switching network is especially important. If the switching network is designed along the lines of a space-division multiplex switching network, each junction point of the bus bar system consisting of feeder lines and trunk lines has a comparator assigned thereto, which compares the addresses of the trunk lines arranged in columns with the routing information contained in the packet message headers. If, simultaneously, several of the auxiliary lines arranged in rows are to be connected through to one of the trunk lines arranged in a column, the order is determined by means of a decision circuit associated to each trunk line. If the order is determined by the spatial arrangement of the feeder lines, each decision circuit cyclically scans all comparators associated thereto, so that a new evaluation of the routing information is not achieved until the complete cycle has finished.

Method of and circuit arrangement for controlling a switching network in

Large-scale time-division switching arrangements often consist of a central switching network and a series of so-called concentrators. For establishing an H1 switching a series of wideband concentrators are connected to a central wideband switching network if the wideband concentrators are of a modular structure and communicate through an internal bus system and an interface circuit with the central wideband switching network connected thereto, a distribution switching in the direction of the subscriber station and a testing of the concentrators while in operation can be effected in a simple way.

Shared lines equipment, especially for B-ISDN switching system

A buffer memory for an input line of a digital interface serves to adapt input data which exhibit large phase fluctuations with respect to the local clock of the interface to this local clock. To this end it is necessary to write the input data with the associated clock into the buffer, the data being read with the local clock. Depending on the phase shifts, write and read operation are then liable to occur simultaneously in border cases. In order to enable the use of conventional components in spite of the described phenomenon, the buffer memory is composed of a number of storage blocks which each comprise the same number of addresses, the storage blocks normally being cyclically addressed in succession. An address spacing monitoring device ensures that read and write operations are always performed only in different storage blocks, so that they can take place simultaneously. When the spacing between read and write operations becomes less than the number of address positions of a storage block due to prolonged, large phase fluctuations so that there is a risk of simultaneous read and write operations within the same block, a read address jump is made in order to address a next or a preceding storage block so that the address is increased again. This address jump takes place only at or directly after the changing over of notably the read address from one storage block to another.

Buffer memory for an input line of a digital interface

A central exchange comprising at its input end a change-over arrangement having a change-over switch for each input line and at its output end a change-over arrangement of an identical structure having a change-over switch for each output line, which are controlled in parallel. Each change-over switch sequentially supplies at its output the channels of a multiplex frame on the different input lines. For each input line a data store and a control store are assigned to the change-over switch at the input end, in a predetermined sequence for each instant, each data store storing the words of all channels of always one input line, but always a different frame. Consequently, all the data stores together contain the words of all the input lines from a number of consecutive frames equal to the number of input lines. The control stores have the same number of addresses as the data store and address these addresses in a similar way, but always shifted through one frame length from data store to data store. This provides a switching matrix in which no blocking occurs and which behaves as a single-stage switching matrix, so that the switching path is controlled without path search.

Digital TDM switching exchange wherein switching is effected by the

A switching exchange in which data on each incoming line are applied to an encoder which produces redundant code words therefrom. The switching matrix is divided into n sub-switching matrices which each transmit a different sub-code word. The outputs of the sub-switching matrices are connected to a decoder which corrects erroneous data words and in addition indicates the occurrence of a fault. Each sub-switching matrix may have its own setting processor receiving identical setting information from a central switching processor. In the event of failure of a sub-switching matrix the decoder can correctly restore the data words. It therefore is possible to effet repair simply replacing the defective sub-switching matrix without switching-off the exchange.

Exchange with error correction

A switching network used to connect a number of input lines to a number of output lines via an internal time-division multiplex line. A memory and a counter for repeatedly and cyclically addressing all the memory locations is provided. An output line which is connected to the internal time-division multiplex line by means of an address decoder, the address decoders being connected to the counter, is assigned to each memory location. The memory receives in each memory location the number assigned to an input line, the output of the memory being connected to each one of the number decoders for each input line, which each time decodes a different number. As a result thereof, after reading of an address, an output line is switched by an address decoder, is connected to the internal time-division multiplex line, this time-division multiplex line being connected to the input line via the number decoder which corresponds to the number stored in this location. When the switching network is used as a concentrator, the input lines, the subscriber's lines and the output lines are preferably the connections to the service modules of a subscriber's station in a remote time-division multiplex transmission system. The switching network is to a large extent of a modular construction and can therefore be easily extended.

Switching network

A light deflector used for tracking a spiral information track alternately and periodically interrupted by data blocks and guide segments arranged within sectors of a rotating record carrier. The light deflector is controlled during the first turn of the information track by a slow analog light deflector having a small stroke and is controlled during the remainder of the recording by a digital light deflector control device having a relatively large stroke.

Electrically controlled adjusting device for a light beam with digital

A system for the position control of a write-read head for information carriers with a magnetic storage layer, having optical servo tracks. The servo tracks consist of periodically interrupted lines, whose period length is constant and whose phase relationship differs for adjacent servo tracks. An optical scanner is connected to the magnetic write-read head and is provided with a diaphragm which transmits at the most one line section and at least one overlap between two adjacent line sections to the scanner.

Magnetic information carrier with optical servo tracks and apparatus for

An optical storage system for the simultaneous or random storage of digital information in a plurality of channels, comprising a rotating storage disc which is scanned by a light beam. The digital information of each channel is stored in points along a spiral track comprising interruptions. A concentrical guide track is associated with each channel. The light beam being focussed onto both tracks of each channel for optical addressing. The light beams of all channels are controlled via deflection systems so that, during the interruptions, they are briefly directed onto the guide tracks while following the spiral tracks. From the radial deviation of the moving disc, measured by way of a detector system, control signals are derived by the deflection systems to compensate for undesired radial motions of the spiral-shaped tracks.

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Quickborn, Germany

Johann E Kruger