International Business Machines Corporation

Globalfoundries Inc.

Advanced Micro Devices Corporation

Johan W Weijtmans

Judson Robert Holt

Brian Joseph Greene

William K Henson

Rohit Pal

Michael D Steigerwalt

Kuldeep Amarnath

Kevin K Chan

Jeffrey Bowman Johnson

Scott D Luning

Dae-Gyu Park

Thomas Safron Kanarsky

Frank Bin Yang

Kevin McStay

Jophy Stephen Koshy

Frank (Bin) Yang

A low energy surface is formed by a high temperature anneal of the surfaces of trenches on each side of a gate stack. The material of the semiconductor layer reflows during the high temperature anneal such that the low energy surface is a crystallographic surface that is at a non-orthogonal angle with the surface normal of the semiconductor layer. A lattice mismatched semiconductor material is selectively grown on the semiconductor layer to fill the trenches, thereby forming embedded lattice mismatched semiconductor material portions in source and drain regions of a transistor. The embedded lattice mismatched semiconductor material portions can be in-situ doped without increasing punch-through. Alternately, a combination of intrinsic selective epitaxy and ion implantation can be employed to form deep source and drain regions.

Self-aligned embedded SiGe structure and method of manufacturing the same

Semiconductor devices with embedded silicon germanium source/drain regions are formed with enhanced channel mobility, reduced contact resistance, and reduced silicide encroachment. Embodiments include embedded silicon germanium source/drain regions with a first portion having a relatively high germanium concentration, e.g., about 25 to about 35 at. %, an overlying second portion having a first layer with a relatively low germanium concentration, e.g., about 10 to about 20 at. %, and a second layer having a germanium concentration greater than that of the first layer. Embodiments include forming additional layers on the second layer, each odd numbered layer having relatively low germanium concentration, at. % germanium, and each even numbered layer having a relatively high germanium concentration. Embodiments include forming the first region at a thickness of about 400 &#x212b; to 28 about 800 &#x212b;, and the first and second layers at a thickness of about 30 &#x212b; to about 70 &#x212b;.

Embedded silicon germanium source drain structure with reduced silicide encroachment and contact resistance and enhanced channel mobility

A semiconductor device and a method of making the device are provided. The method can include forming a gate conductor overlying a major surface of a monocrystalline semiconductor region and forming first spacers on exposed walls of the gate conductor. Using the gate conductor and the first spacers as a mask, at least extension regions are implanted in the semiconductor region and dummy spacers are formed extending outward from the first spacers. Using the dummy spacers as a mask, the semiconductor region is etched to form recesses having at least substantially straight walls extending downward from the major surface to a bottom surface, such that a substantial angle is defined between the bottom surface and the walls. Subsequently, the process is continued by epitaxially growing regions of stressed monocrystalline semiconductor material within the recesses. Then the dummy spacers are removed and the transistor can be completed by forming source/drain regions of the transistor that are at least partially disposed in the stressed semiconductor material regions.

Transistor having V-shaped embedded stressor

Growing community of inventors

Hopewell Junction, NY, United States of America

Johan W Weijtmans