Stichting Imec Nederland

Johan Van Den Heuvel

Paul Mateman

Yao-Hong Liu

Gaurav Singh

Elbert Bechthum

Yuming He

Erwin Allebes

A polar transmitter is provided. The polar transmitter includes a baseband generation unit configured to generate phase data bits and amplitude data bits of an output pulse. The polar transmitter further includes a bandwidth control unit downstream to the baseband generation unit configured to regulate the width of the output pulse. Moreover, the polar transmitter includes a pulse shaping unit downstream to the bandwidth control unit configured to generate a predefined amplitude envelope of the output pulse. In this context, the pulse shaping unit includes a delay-line with a plurality of taps, where each tap output is configured to be amplitude weighted in order to generate the amplitude envelope of the output pulse.

Asynchronous polar transmitter and operation method thereof

An all-digital phase locked loop (ADPLL) is provided. The ADPLL comprises a pattern generator adapted to generate a frequency control word (FCW) based on a predefined setting and a system clock. In addition, the ADPLL comprises a phase accumulator adapted to translate the FCW into a phase trajectory. The ADPLL further comprises a phase comparator adapted to generate a phase error signal representing a difference between the phase trajectory and the phase of an output oscillation frequency. Moreover, the ADPLL comprises a controller adapted to control a phase of the output oscillation frequency with respect to the phase trajectory.

Systems and methods for all-digital phase locked loop

A circuit for facilitating random edge injection locking of an oscillator comprises a clock signal and a digitally controlled delay line, where the digitally controlled delay line is configured to delay the clock signal, thereby generating a delayed clock signal. The circuit further comprises an edge selector configured to generate a phase select signal with a random pulse sequence. Moreover, the circuit comprises a pulse generator downstream to the digitally controlled delay line configured to generate injection pulses from the delayed clock signal for at least two phases of the oscillator based on the phase select signal.

Circuit and method for random edge injection locking

A radio frequency, RF, transmitter, comprises a digitally controlled oscillator, DCO, configured to generate an RF signal; and digital modulation circuitry connected to the DCO for modulation of the RF signal, and driven by an RF clock signal derived from the RF signal, wherein the digital modulation circuitry comprises a module configured to apply a compensation for modulation jitter due to the modulation circuitry being driven by the RF clock signal and a compensation for DCO non-linearity.

RF transmitter

A signal generator has a nominal frequency control input and a modulation frequency control input and comprises an oscillator, with a first set of capacitors at least partially switchably connectable for adjusting a frequency of the oscillator as part of a phase-locked loop, and a second set of capacitors comprised in a modulation stage of the oscillator, switchably connectable for modulating the frequency and controlled by the modulation frequency control input; a modulation gain estimation stage configured to determine a frequency-to-capacitor modulation gain; and a modulation range reduction module configured for clipping a modulation range of the oscillator to a range achievable using the second set of capacitors, using the modulation gain averaging out, in time, a phase error caused by the said clipping; and mimicking the said clipping, additively output to the nominal frequency control input to compensate said PLL for the said modulation.

Signal generator

A signal generator comprises (i) a first set of capacitors at least partially switchably connectable for adjusting a frequency of an oscillator as part of a phase-locked loop and (ii) a second set of capacitors comprised in one or more oscillator control subsystems. A method of controlling the signal generator comprises: (i) acquiring a frequency lock in the phase-locked loop, (ii) calculating, in conjunction with the acquiring of the frequency lock, a systematic capacitance error of the first set of capacitors due to process, voltage, and temperature variations based on the frequency of the oscillator and a switching state of the first set of capacitors, and (iii) calibrating the one or more oscillator control subsystems using the systematic capacitance error, thereby compensating for process, voltage, and temperature variations common between the first set of capacitors and the second set of capacitors.

The present disclosure relates to a Digital Phase Locked Loop (DPLL) for phase locking an output signal to a reference clock signal. The DPLL comprises a phase detector for detecting a phase error of a feedback signal with respect to the reference clock signal. The DPLL comprises a digitally controlled oscillator for generating the output signal based at least on a frequency control word and at least one control signal representative of the phase error. The phase detector comprises an integer circuit for generating a first control signal representative of an integer phase error. The phase detector comprises a fractional circuit comprising a Time-to-Digital Converter (TDC) for processing the feedback signal and a delayed reference clock signal. The fractional circuit is provided for generating from the TDC output a second control signal representative of a fractional phase error. The DPLL comprises an unwrapping unit for unwrapping the TDC output.

Digital phase locked loop and method for operating the same

Embodiments described herein include a receiver, a method, and a plurality of high-pass filters for demodulating a radio frequency (RF) signal. An example receiver includes a plurality of high-pass filters. The receiver includes a demodulator configured to demodulate an RF signal received at an input of the demodulator and configured to output a demodulated signal. The receiver also includes a plurality of high-pass filters connected to an output of the demodulator. The plurality of high-pass filters are configured to receive the demodulated signal and configured to high-pass filter the demodulated signal. The plurality of high-pass filters are configured to operate with a first set of filter responses during a first time period of the demodulated signal and configured to operate with a second set of filter responses during a second time period of the demodulated signal.

Receiver including a plurality of high-pass filters

An all-digital phase-locked loop (AD-PLL) and related methods and computer readable medium are provided. The AD-PLL comprises a reference phase generator for receiving a digital signal and splitting the digital signal into an integer part and a fractional part, an estimator block for estimating a control signal, and a digital-to-time converter for receiving the estimated control signal and a reference clock signal and for deriving a delayed reference clock signal. The AD-PLL also includes a time-to-digital converter for receiving the delayed reference clock signal and a desired clock signal phase, and for deriving a fractional phase error. The estimator block receives the fractional phase error and determines the estimated control signal by correlating the fractional phase error with the fractional part, yielding a correlated signal, multiplying the correlated signal with its absolute value, and integrating the outcome of the multiplying to obtain the estimated control signal.

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Geldrop, Netherlands

Johan Van Den Heuvel