Imec Vzw

Imec

Vrije Universiteit Brussel

Johan Swerts

Sebastien Couet

Sven Van Elshocht

Jorge Adrian Kittl

Gouri Sankar Kar

Mihaela Ioana Popovici

Christoph Adelmann

Min-Soo Kim

Tsann Lin

Mauricio Manfrini

Christian Caillat

Geoffrey Pourtois

Trong Huynh Bao

Annelies Delabie

Hanns Christoph Adelmann

Manu Komalan Perumkunnil

Sushil Sakhare

Kevin Garello

Robert Carpenter

Kiroubanand Sankaran

Malgorzata Pawlak

Kazuyuki Tomida

Sofie Mertens

Jorge Kittl

The disclosed technology relates generally to the field of magnetic devices, in particular to magnetic memory devices or logic devices. The disclosed technology presents a magnetic structure for a magnetic device, wherein the magnetic structure comprises a magnetic reference layer (RL); a spacer provided on the magnetic RL, the spacer comprising a first texture breaking layer provided on the magnetic RL, a magnetic bridge layer provided on the first texture breaking layer, and a second texture breaking layer provided on the magnetic bridge layer. Further, the magnetic structure comprising a magnetic pinned layer (PL) or hard layer (HL) provided on the spacer, wherein the magnetic RL and the magnetic PL or HL are magnetically coupled across the spacer through direct exchange interaction.

Multilayer spacer between magnetic layers for magnetic device

The disclosed technology relates generally to semiconductor devices and more particularly to magnetic tunnel junction devices. According to an aspect, an MTJ device comprises a spin-orbit-torque (SOT)-layer. The MTJ device additionally comprises a first free layer, a second free layer, a reference layer and a tunnel barrier layer arranged between the second free layer and the reference layer. The MTJ device further comprises a spacer layer arranged as an interfacial layer between the first free layer and the second free layer. The SOT-layer is adapted to switch a magnetization direction of the first free layer through SOT. The first free layer is adapted to generate a magnetic stray field acting on the second free layer such that a magnetization direction of the second free layer is responsive to a magnetization direction of the first free layer. According to another aspect, a circuit comprises the MTJ device.

Magnetic tunnel junction device

The disclosed technology relates generally to semiconductor devices, and more particularly to a layer stack for a magnetic tunnel junction (MTJ) device, and a method of forming the same. According to an aspect, a layer stack for a (MTJ) device comprises a seed layer structure, a pinning layer structure arranged above the seed layer structure, and above the pinning layer structure a Fe-comprising reference layer structure and a free layer structure separated by a tunnel barrier layer. The seed layer structure comprises a Ru-comprising layer and a Cr-comprising layer. The Cr-comprising layer forms an upper layer of the seed layer structure.

Layer stack for magnetic tunnel junction device

According to an example embodiment an MTJ unit is provided. The MTJ unit includes: a first MTJ comprising a first free layer, a first tunnel barrier layer and a first reference layer. The first MTJ is switchable between a parallel state and an anti-parallel state through spin-torque transfer (STT). The MTJ unit comprises a second MTJ arranged above the first MTJ and comprising, a second reference layer, a second tunnel barrier layer and a second free layer. The second MTJ is switchable between a parallel state and an anti-parallel state through STT. The MTJ unit comprises a pinning layer arranged between the first reference layer and the second reference layer and configured to fix a magnetization direction of the first reference layer and the second reference layer.

Spin-torque transfer switchable magnetic tunnel junction unit and a memory device

The disclosed technology generally relates semiconductor devices, and relates more particularly to a spin transfer torque device, a method of operating the spin-transfer torque device and a method of fabricating the spin-transfer torque device. According to one aspect, a spin-transfer torque device includes a magnetic flux guide layer and a set of magnetic tunnel junction (MTJ) pillars arranged above the magnetic flux guide layer. Each one of the pillars includes a separate free layer, a separate tunnel barrier layer and a separate reference layer. A coupling layer is arranged between the magnetic flux guide layer and the MTJ pillars, wherein a magnetization of the separate free layer of each of the each of the MTJ pillars is coupled, parallel or antiparallel, to a magnetization of the magnetic flux guide layer through the coupling layer.

Spin-transfer torque device

The disclosed technology generally relates to a magnetoresistive device and more particularly to a magnetoresistive device comprising chromium. According to an aspect, a method of forming a magnetoresistive device comprises forming a magnetic tunnel junction (MTJ) structure over a substrate. The MTJ structure includes, in a bottom-up direction away from the substrate, a free layer, a tunnel barrier layer and a reference layer. The method additionally includes forming a pinning layer over the MTJ structure, wherein the pinning layer pins a magnetization direction of the reference layer. The method additionally includes forming capping layer comprising chromium (Cr) over the pinning layer. The method further includes annealing the capping layer under a condition sufficient to cause diffusion of Cr from the capping layer into at least the pinning layer. According to another aspect, a magnetoresistive device is formed according to the method.

Magnetoresistive device comprising chromium

The disclosed technology generally relates to semiconductor devices and more particularly to semiconductor devices comprising a magnetic tunnel junction (MTJ). In an aspect, a method of forming a magnetoresistive random access memory (MRAM) includes forming a layer stack above a substrate, where the layer stack includes a ferromagnetic reference layer, a tunnel barrier layer and a ferromagnetic free layer and a spin-orbit-torque (SOT)-generating layer. The method additionally includes, subsequent to forming the layer stack, patterning the layer stack to form a MTJ pillar.

Magnetic random access memory device having magnetic tunnel junction

The disclosed technology generally relates to magnetic devices, and more particular to a magnetic structure, and a magnetic tunnel junction device and a magnetic random access memory including the magnetic structure. According to an aspect, a magnetic structure for a magnetic tunnel junction (MTJ) device includes a free layer, a tunnel barrier layer, a reference layer, a hard magnetic layer, and an inter-layer stack arranged between the hard magnetic layer and the reference layer. The inter-layer stack includes a first ferromagnetic sub-layer, a second ferromagnetic sub-layer and a non-magnetic spacer sub-layer. The non-magnetic spacer sub-layer is arranged in contact with and between the first ferromagnetic sub-layer and the second ferromagnetic sub-layer and is adapted to provide a ferromagnetic coupling of a magnetization of the first ferromagnetic sub-layer and a magnetization of the second ferromagnetic sub-layer. A magnetization direction of the reference layer is fixed by the hard magnetic layer and the inter-layer stack.

Magnetic junction device having an inter-layer stack between a hard magnetic layer and a reference layer, and associated magnetic random access memory

The disclosed technology generally relates to forming a semiconductor structure and more particularly to forming a stack of layers of a semiconductor structure using a sacrificial layer that is removed during deposition of a functional layer. In one aspect, the disclosed technology relates to a method of protecting a top surface of a layer in a semiconductor structure. The method comprises: providing the layer on a substrate, the layer having an initial thickness and an initial composition; forming a sacrificial metal layer on and in contact with the layer, the sacrificial metal layer comprising a light metal element; and depositing by physical vapor deposition a functional metal layer on and in contact with the sacrificial metal layer. The sacrificial metal layer is removed by sputtering during the deposition of the functional metal layer, such that an interface is formed between the layer and the functional metal layer. The sacrificial metal layer protects the layer during the deposition of the functional metal layer, such that the layer has a final thickness which substantially matches the initial thickness and a final composition which substantially matches the initial composition.

Method of forming a stack of layers using a sacrificial layer

The disclosed technology relates generally to magnetic devices, and more particularly to spin torque majority gate devices such as spin torque magnetic devices (STMG), and to methods of fabricating the same. In one aspect, a majority gate device includes a plurality of input zones and an output zone. A magnetic tunneling junction (MTJ) is formed in each of the input zones and the output zone, where the MTJ includes a non-magnetic layer interposed between a free layer stack and a hard layer. The free layer stack in turn includes a bulk perpendicular magnetic anisotropy (PMA) layer on a seed layer, a magnetic layer formed on and in contact with the bulk PMA layer, and a non-magnetic layer formed on the magnetic layer. Each of the bulk PMA layer and the seed layer is configured as a common layer for each of the input zones and the output zone.

Spin torque majority gate device

The disclosed technology generally relates to magnetic memory devices, and more particularly to spin transfer torque magnetic random access memory (STT-MRAM) devices having a magnetic tunnel junction (MTJ), and further relates to methods of fabricating the STT-MRAM devices. In an aspect, a magnetoresistive random access memory (MRAM) device has a magnetic tunnel junction (MTJ). The MTJ includes a magnetic reference layer including CoFeB, a magnetic free layer comprising CoFeB, and a barrier layer including MgO. The barrier layer is interposed between the magnetic reference layer and the magnetic free layer. The barrier layer has a thickness adapted to tunnel electrons between the magnetic reference layer and the magnetic free layer sufficient to cause a change in the magnetization direction of the variable magnetization under a bias. The MTJ further comprises a buffer layer comprising one or more of Co, Fe, CoFe and CoFeB, where the buffer layer is doped with one or both of C and N.

Magnetic memory device having buffer layer

The disclosure provides a method for producing a stack of layers on a semiconductor substrate. The method includes producing a substrate a first conductive layer; and producing by ALD a sub-stack of layers on said conductive layer, at least one of said layers of the sub-stack being a TiOlayer, the other layers of the sub-stack being layers of a dielectric material having a composition suitable to form a cubic perovskite phase upon crystallization of said sub-stack of layers. Crystallization is obtained via heat treatment. When used in a metal-insulator-metal capacitor, the stack of layers can provide improved characteristics as a consequence of the TiOlayer being present in the sub-stack.

Metal-insulator-metal capacitor and method for manufacturing thereof

A method for forming a noble metal layer by Plasma Enhanced Atomic Layer Deposition (PE-ALD) is disclosed. The method includes providing a substrate in a PE-ALD chamber, the substrate comprising a first region having an exposed first material and a second region having an exposed second material. The first material comprises a metal nitride or a nitridable metal, and the second material comprises a non-nitridable metal or silicon oxide. The method further includes depositing selectively by PE-ALD a noble metal layer on the second region and not on the first region, by repeatedly performing a deposition cycle including (a) supplying a noble metal precursor to the PE-ALD chamber and contacting the noble metal precursor with the substrate in the presence of a carrier gas followed by purging the noble metal precursor, and (b) exposing the substrate to plasma while supplying ammonia and the carrier gas into the PE-ALD chamber.

Method for selectively depositing noble metals on metal/metal nitride substrates

Methods of manufacturing metal-insulator-metal capacitor structures, and the metal-insulator-metal capacitor structures obtained, are disclosed. In one embodiment, a method includes providing a substrate, forming on the substrate a first metal layer comprising a first metal, and using atomic layer deposition with an HO oxidant to deposit on the first metal layer a protective layer comprising TiO. The method further includes using atomic layer deposition with an Ooxidant to deposit on the protective layer a dielectric layer of a dielectric material, and forming on the dielectric layer a second metal layer comprising a second metal. In another embodiment, a metal-insulator-metal capacitor includes a bottom electrode comprising a first metal, a protective layer deposited on the bottom electrode and comprising TiO, a dielectric layer deposited on the protective layer and comprising a dielectric material, and a top electrode formed on the dielectric layer and comprising a second metal.

Growing community of inventors

Kessel-lo, Belgium

Johan Swerts