Alcatel Lucent

Alcatel N.v.

Imec

Johan J Haspeslagh

Peter P Reusens

Thierry Pollet

Michaël Andries Thomas Beck

Eric Borghs

Stefaan Margriet Van Hoogenbemt

Marc R De Langhe

Steven Gerard Boucqué

Eric Fran Elisa Borghs

Michaël Beck

Steven Boucqué

A device and method for exchanging data frames are disclosed. In one aspect, the device exchanges data between a WAN and one or more LAN segments in an optimized way leading to a better quality of experience for the user. The device comprises an interface exchanging data frames over an access network, at least a first and second subnet interface exchanging data frames and arranged for being coupled to a network, a memory storing classification rules, a classification agent extracting information from an incoming data frame and applying the rules to the extracted information to determine the interface via which the incoming data frame is to be forwarded, and a Quality of Service monitoring agent for retrieving Quality of Service information from the subnet interfaces and dynamically updating the classification rules according to the QoS information.

Gateway with improved QoS awareness

A digital phase locked loop arrangement is used in a desynchronizer demapping a plesiochronous stream from a synchronous bitstream is disclosed to remove jitter due to overhead gapping from the plesiochronous stream. To this end the part of the synchronous bitstream constituting the plesiochronous stream is written into a buffer memory (BUFF), the write address (WRADDR) of which is incremented at the rate of this plesiochronous part. The read address (RDADDR) for the buffer memory (BUFF) is derived from the write address (WRADDR) in the digital phase locked loop arrangement. Herein, a negative feedback for byte justifications in the synchronous bitstream and a positive feedback for bit justifications therein is provided so that byte justifications give rise to a lower change in the incrementing rate of the read address (RDADDR) but of longer duration, whereas bit justifications give rise to an increased change in this incrementing rate but of shorter duration.

Digital phase-locked loop arrangement for use in a desynchronizer

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Heverlee, Belgium

Johan J Haspeslagh