Freescale Semiconductor,inc.

Jogendra C Sarker

Ravindraraj Ramaraju

Prashant U Kenkare

David R Bearden

Hamed Ghassemi

Eric V Fiene

Vu N Tran

A memory management unit can receive an address associated with a page size that is unknown to the MMU. The MMU can concurrently determine whether a translation lookaside buffer data array stores a physical address associated with the address based on different portions of the address, where each of the different portions is associated with a different possible page size. This provides for efficient translation lookaside buffer data array access when different programs, employing different page sizes, are concurrently executed at a data processing device.

Multiple page size memory management unit

A method and data processing system for accessing an entry in a memory array by placing a tag memory unit () in parallel with an operand adder circuit () to enable tag lookup and generation of speculative way hit/miss information () directly from the operands () without using the output sum of the operand adder. PGZ-encoded address bits (0:51) from the operands () are applied with a carry-out value (Cout) to a content-addressable memory array () to generate two speculative hit/miss signals. A sum value (EA) computed from the least significant base and offset address bits determines which of the speculative hit/miss signals is selected for output ().

Memory management unit tag memory

A memory includes a row decoder, column logic, and a memory array having a plurality of memory cells arranged in rows and columns. A plurality of write word lines are coupled to the row decoder. A plurality of complementary write word lines is coupled to the row decoder. A plurality of read bit lines is coupled to the column logic. A plurality of write bit lines is coupled to the column logic. A plurality of column decoded write enable lines is coupled to the column logic. Each memory cell of the plurality of memory cells is coupled to a corresponding write control circuit. Each write control circuit comprises a transmission gate coupled between a column decoded write enable line and an access transistor of a memory cell. The transmission gate is controlled by a write word line signal.

Circuit for preventing a dummy read in a memory

A translation look-aside buffer (TLB) has a TAG memory for determining if a desired translated address is stored in the TLB. A TAG portion is compared to contents of the TAG memory without requiring a read of the TAG memory because the TAG memory has a storage portion that is constructed as a CAM. For each row of the CAM a match determination is made that indicates if the TAG portion is the same as contents of the particular row. A decoder decodes an index portion and provides an output for each row. On a per row basis the output of the decoder is logically combined with the hit/miss signals to determine if there is a hit for the TAG memory. If there is a hit for the TAG memory, a translated address corresponding to the index portion of the address is then output as the selected translated address.

Translation look-aside buffer with a tag memory and method therefor

A dual-port memory includes a plurality of memory cells coupled to a row decoder and column logic. Each memory cell includes two storage nodes, where each storage node is coupled to a bit line via an access transistor. Each memory cell also includes a logic gate for logically combining a word line signal with a column address signal and providing the resulting output signal to the gates of the access transistors. In one embodiment, the logic gate is a NOR logic gate and in another embodiment, the logic gate is a transmission gate. This prevents a potential read disturb problem with unselected memory cells of a row. This also reduces power consumption in the memory.

Dual-port static random access memory having improved cell stability and write margin

A SRAM () includes a SRAM cell (), the cell () includes a first storage node (N), a second storage node (N), and a cross coupled latch () including a first primary source current path to the first storage node, a first primary sink current path to the first storage node, a second primary source current path to the second storage node, a second primary sink current path to the second storage node, a fifth primary current path to the first storage node, and a sixth primary current path to the second storage node. During standby and/or a read operation of the SRAM cell (), one of the fifth primary current path and the sixth primary current path is conductive. During a write operation, the fifth primary current path and the sixth primary current path are non-conductive.

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Austin, TX, United States of America

Jogendra C Sarker