Imec

Epigan Nv

Soitec Belgium

Katholieke Universiteit Leuven, Ku Leuven R&d

Interuniversitair Microelektronica Centrum (imec)

Imec Vzw

Soitec

Katholieke Universiteit Leuven

Joff Derluyn

Ionut Radu

Marianne Germain

Stefan Degroote

Maarten Leys

Gustaaf Regina Borghs

Marleen Van Hove

Christelle Veytizou

Farid Medjdoub

Joachim John

Steven Boeykens

Anne Lorenz

Roland Pusche

Germain Marianne

A high electron mobility transistor for analog applications comprising: a substrate; an epitaxial III-N semiconductor layer stack on top of said substrate, said epitaxial III-N semiconductor layer stack comprising: a first active III-N layer; and a second active III-N layer comprising a recess; with a two dimensional Electron Gas in between III-N; a gate on top of said epitaxial III-N semiconductor layer stack; and a passivation stack between said epitaxial III-N semiconductor layer stack and said gate, wherein said passivation stack comprises an electron accepting dielectric layer adapted to deplete said two dimensional Electron Gas when said gate is not biased; wherein said electron accepting dielectric layer extends in said recess and comprises magnesium nitride doped with silicon and/or aluminum.

High electron mobility transistor

A system for in-situ measurement of a curvature of a surface of a wafer comprises: a multiwavelength light source module, adapted to emit incident light comprising a plurality of wavelengths; an optical setup configured to combine the incident light into a single beam and to guide the single beam towards a surface of a wafer such that the single beam hits the surface at a single measuring spot on the surface; and a curvature determining unit, configured to determine a curvature of the surface of the wafer from reflected light corresponding to the single beam being reflected on the surface at the single measuring spot.

Wafer surface curvature determining system

A semiconductor structure includes a buffer layer stack comprising a plurality of III-V material layers, and the buffer layer stack includes at least one layered substructure. Each layered substructure comprises a compressive stress inducing structure between a respective first buffer layer and a respective second buffer layer positioned higher in the buffer layer stack than the respective first buffer layer. A lower surface of the respective second buffer layer has a lower Al content than an upper surface of the respective first buffer layer. An active semiconductor layer of the III-V type is provided on the buffer layer stack. The surface of the respective relaxation layers is sufficiently rough to inhibit the relaxation of the respective second buffer layer, and comprises a Root Mean Square (RMS) roughness larger than 1 nm. A method is provided for producing the semiconductor structure.

Semiconductor structure comprising an active semiconductor layer of the III-V type on a buffer layer stack and method for producing semiconductor structure

A device comprising a III-N layer stack featuring a two-dimensional electron gas is disclosed, comprising: &#x2014;a III-N layer; &#x2014;a AI-III-N layer on top of the III-N layer; &#x2014;a passivation layer on top of said AI-III-N layer, the passivation layer comprising Silicon Nitride (SiN); wherein said passivation layer comprises a fully crystalline sub layer at the AI-III-N interface and at least part of the fully crystalline sub layer comprises Al and/or B; and associated methods for manufacturing the device.

Device comprising a III-N layer stack with improved passivation layer and associated manufacturing method

Disclosed are methods of growing III-V epitaxial layers on a substrate, semiconductor structures thus obtained, and devices comprising such semiconductor structures. An example semiconductor substrate includes a substrate and a buffer layer on top of the substrate, where a conductive path is present between the substrate and buffer layer. A conductive path may be present in the conductive interface, and the conductive path may be interrupted by one or more local electrical isolations. The local electrical isolation(s) may be positioned with the device such that at least one of the local electrical isolation(s) is located between a high voltage terminal and a low voltage terminal of the device.

Method for growing III-V epitaxial layers

Disclosed are methods of growing III-V epitaxial layers on a substrate, a semiconductor structure comprising a substrate, a device comprising such a semiconductor structure, and an electronic circuit. Group III-nitride devices, such as, for example, high-electron-mobility transistors, may include a two-dimensional electron gas (2DEG) between two active layers. For example, the 2DEG may be between a GaN layer and a AlGaN layer. These transistors may work in depletion-mode operation, which means the channel has to be depleted to turn the transistor off. For certain applications, such as, for example, power switching or integrated logic, negative polarity gate supply is undesired. Transistors may then work in enhancement mode (E-mode).

Method for growing III-V epitaxial layers and semiconductor structure

A semiconductor device is disclosed. In one aspect, the device has a first and second active layer on a substrate, the second active layer having a higher bandgap than the first active layer, being substantially Ga-free and including at least Al. The device has a gate insulating layer on a part of the second active layer formed by thermal oxidation of a part of the second active layer. The device has a gate electrode on at least a part of the gate insulating layer and a source electrode and drain electrode on the second active layer. The device has, when in operation and when the gate and source electrode are at the same voltage, a two-dimensional electron gas layer between the first and second active layer only outside the location of the gate electrode and not at the location of the gate electrode.

Method of forming a semiconductor device

A method for manufacturing a III-V CMOS device is disclosed. The device includes a first and second main contact and a control contact. In one aspect, the method includes providing the control contact by using damascene processing. The method thus allows obtaining a control contact with a length of between about 20 nm and 5 &#x3bc;m and with good Schottky behavior. Using low-resistive materials such as Cu allows reducing the gate resistance thus improving the high-frequency performance of the III-V CMOS device.

Damascene contacts on III-V CMOS devices

A method is disclosed for producing Group III-N field-effect devices, such as HEMT, MOSHFET, MISHFET or MESFET devices, comprising two active layers, e.g. a GaN/AlGaN layer. The method produces an enhancement mode device of this type, i.e. a normally-off device, by providing a passivation layer on the AlGaN layer, etching a hole in the passivation layer and not in the layers underlying the passivation layer, and depositing the gate contact in the hole, while the source and drain are deposited directly on the passivation layer. The characteristics of the active layers and/or of the gate are chosen such that no two-dimensional electron gas layer is present underneath the gate, when a zero voltage is applied to the gate. A device with this behavior is also disclosed.

Enhancement mode field effect device and the method of production thereof

Enhancement mode semiconductor device

In the preferred embodiments, a method to reduce gate leakage and dispersion of group III-nitride field effect devices covered with a thin in-situ SiN layer is provided. This can be obtained by introducing a second passivation layer on top of the in-situ SiN-layer, in combination with cleaning of the in-situ SiN before gate deposition and before deposition of the second passivation layer.

Surface treatment and passivation of AlGaN/GaN HEMT

The present invention recites a new method for manufacturing Group III-N field-effect devices, such as HEMT, MOSHFET, MISHFET devices or MESFET devices, grown by Metal-Organic Vapor Phase Expitaxy, with higher performance (power), by covering the surface with a thin SiN layer on the top AlGaN layer, in the reactor where the growth takes place at high temperature, prior cooling down the structure and loading the sample out of the reactor, as well as a method to produce some HEMT transistors on those heterostructures, by depositing the contact on the surface without any removal of the SiN layer by MOCVD. The present invention recites also a device.

Growing community of inventors

Sint-Joris-Weert, Belgium

Joff Derluyn