Cadence Design Systems, Inc.

Joezac John Zachariah

Vinaya Kumar Singh

Amir Lehavot

Axel Siegfried Scherer

Jose Barandiaran

An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which an over-constrained event occurs; identification of a minimum subset of constraints that will cause an over-constrained event to occur; signal ports having an associated signal that can not switch between different signal states; whether a triggering signal event has occurred during the evaluation; indicating whether constraints in the evaluation are realizable, etc. Novel approaches for detecting and obtaining the useful information also are described.

Automated debugging method for over-constrained circuit verification environment

Automated debugging method and system for over-constrained circuit verification environment

Method for providing information associated with an over-constrained event in verification of a circuit design

Method for checking a status of a signal port to identify an over-constrained event

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Noida, India

Joezac John Zachariah