Infineon Technologies Richmond, LP

Other

Infineon Technologies North America Corp.

Joerg Wohlfahrt

Dieter Rathei

Thomas Hladschik

Peter Oswald

Jens Holzhaeuser

Thomas Giegold

A method of analyzing cells of a memory device is disclosed. Generally, a plurality of fail signatures is generated, wherein each fail signature is associated with a type of failure. Voltages according to a plurality of test patterns are applied to nodes of a cell of the memory device. Fail data of the cell for the plurality of patterns is then analyzed, and a fail signature of the cell is determined. A type of failure of the cell based upon the plurality of fail signatures is then determined. A system for analyzing cells of a memory device is also disclosed. The system generally includes a plurality of probes applying different voltages to a cell of the memory device. A control circuit varies the voltages applied to the cell, and compares the failures of the cell as the test voltage applied to the cell is varied to an artificial bit map. Finally, an output device generates an output indicating a type of failure of the cell.

Method of and system for analyzing cells of a memory device

A method for classifying patterns of failcodes on a semiconductor wafer, in accordance with the present invention, includes determining failcodes for chips on the wafer and checking adjacent chips for each chip on the wafer having a failcode to determine a failcode pattern having a defined number of chips.

Method and apparatus for fast automated failure classification for semiconductor wafers

The present invention includes a method for characterizing semiconductor failure. The method includes determining the dimensions of certain characteristics of a memory chip. The method defines a group of characteristics for a semiconductor of given dimensions. The method defines a ratio based on variables supplied by production test systems. By comparing a set of characteristics for a specific semiconductor to the ratio to determine the dominant type of failure on the semiconductor chip. The invention is an efficient method of obtaining information regarding the types of failures common on semiconductor chips.

Method for efficient analysis semiconductor failures

A method for forming uniform-depth recesses across areas of different trench density, in accordance with the present invention, includes providing a substrate having trenches formed therein. The substrate includes regions of different trench density. The trenches are filled with a first filler material, and the first filler material is removed from a surface of the substrate. A second filler material is formed over the surface of the substrate such that the depth of the second filler material is substantially uniform across the regions of different trench density. Recesses are formed in the trenches such that the recess depth below the surface of the substrate is substantially uniform across the regions

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Taipei, Taiwan

Joerg Wohlfahrt