Globalfoundries Inc.

Joerg Schmid

Ralf Van Bentum

Jongsin Yun

Seunghwan Seo

Peter Baars

Hans-Juergen Thees

A semiconductor structure including a nonvolatile memory cell element including an active region formed in a semiconductor material, a select gate structure, a dummy control gate structure and a transfer gate structure is provided. Additionally, an electrically insulating structure extending around each of the select gate structure, the dummy control gate structure and the transfer gate structure is provided. The dummy control gate structure is removed, wherein a first recess is formed in the semiconductor structure. After removing the dummy gate structure, a charge trapping layer and a layer of a control gate electrode material are deposited over the semiconductor structure. Portions of the charge trapping layer and the layer of the control gate electrode material over the electrically insulating structure are removed. Portions of the charge trapping layer and the layer of control gate electrode material in the recess provide a control gate structure of the nonvolatile memory cell.

Semiconductor structure including a nonvolatile memory cell having a charge trapping layer and method for the formation thereof

A method includes providing a semiconductor structure. The semiconductor structure includes a first transistor region, a second transistor region and a silicon dioxide layer on the first transistor region and the second transistor region. A layer of a high-k dielectric material is deposited on the silicon dioxide layer. A layer of a first metal is formed over the second transistor region. The layer of first metal does not cover the first transistor region. After the formation of the layer of the first metal, a layer of a second metal is deposited over the first transistor region and the second transistor region. A first annealing process is performed. The first annealing process initiates a scavenging reaction between the second metal and silicon dioxide from a portion of the silicon dioxide layer on the first transistor region. After the annealing process, a ferroelectric transistor dielectric is formed over the first transistor region.

Semiconductor structure including a ferroelectric transistor and method for the formation thereof

An illustrative semiconductor structure described herein includes a substrate including a logic transistor region, a ferroelectric transistor region and an input/output transistor region. A logic transistor is provided at the logic transistor region. The logic transistor includes a gate dielectric and a gate electrode. An input/output transistor is provided at the input/output transistor region. The input/output transistor includes a gate dielectric and a gate electrode. The gate dielectric of the input/output transistor has a greater thickness than the gate dielectric of the logic transistor. A ferroelectric transistor is provided at the ferroelectric transistor region. The ferroelectric transistor includes a ferroelectric dielectric and a gate electrode. The ferroelectric dielectric is arranged between the ferroelectric transistor region and the gate electrode of the ferroelectric transistor.

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Dresden, Germany

Joerg Schmid