Infineon Technologies Ag

Qimonda Ag

Joerg Kliewer

Manfred Proell

Stephan Schroeder

Ralf Schneider

Herbert Benzinger

Wolfgang Ruf

Martin Versen

Manfred Dobler

Georg Erhard Eggers

Klaus Nierle

Hermann Hass

An apparatus and methods for testing an integrated device comprising memory a test device are provided. At least two data inputs of the memory are coupled to a data output of the test device. As an alternative, at least two data outputs of the memory are coupled to a data input of the test device. Test data are transferred from the test device to the memory chip and written to memory cells of the memory. Data are read from the memory cells of the memory and transferring from the memory to the test device. The data read from the memory chip are compared with the test data written to the memory in order to identify faults of the memory.

Method and apparatus for testing a memory chip using a common node for multiple inputs and outputs

Method and system for testing an integrated circuit

A semiconductor memory and a test method for testing whether word line segments () are floating after an activation operation or a deactivation operation is disclosed. For this purpose, the charge-reversal current (I) that occurs in the event of a word line segment () being subjected to charge reversal or a charge quantity (Q) which is fed to the word line () or conducted away from the word line segment () as a result of this is measured. If, upon activation or deactivation of a word line segment (), the measured charge-reversal current (I) or the corresponding charge quantity (Q) is less than a lower limit value, it is ascertained that the relevant word line segment () has a defective contact terminal. In this way, high-impedance or defective contact hole fillings can thereby be identified and the associated word line segments () can be replaced by redundant word lines.

Integrated semiconductor memory comprising at least one word line and method

A semiconductor memory includes storage cells () that have storage capacitors and transistors with an electrode, which is electrically biasable with two different electrical potentials (VV) in order to open and close the transistor. The electrode potential (V) intended for the off state of the transistor is a temperature-dependent potential, the value of which is controlled temperature-dependently by the semiconductor memory () so that the second electrical potential (V) becomes more different from the first electrical potential (V) as the temperature (T) increases.

Semiconductor memory and method for operating a semiconductor memory

The invention relates to a RAM store having a shared SA structure, in which sense amplifiers (SA) arranged in SA strips () between two respective adjacent cell blocks are used by a plurality of bit line pairs () from the adjacent cell blocks and the bit line pairs () have respective charge equalization circuits individually associated with them for the purpose of performing charge equalization between the bit line halves of the bit line pairs () in a precharge phase, where a shorting transistor () is provided which, when prompted by a control signal (EQLx), connects the bit line halves (BLT, BLC) of the bit line pairs () which are in the precharge phase to one another. The shorting transistor () is arranged in or on the respective sense amplifier (SA) jointly for all bit line pairs () which can be connected to a repetitive sense amplifier (SA), and it can be switched by a separate shorting control signal (EQLx) via a dedicated control line ().

RAM store and control method therefor

An integrated semiconductor memory includes a DRAM memory, in which primary sense amplifiers (SA) are coupled to a bit line (BL) of a respective cell block and can be connected to a common local data line (LDQ) by means of a respective assigned CSL switch in response to a CSL signal and in which an MDQ/LDQ switch arrangement connects a main data line (MDQ) to the local data line (LDQ) of a respective cell block in response to an MDQ/LDQ switch signal. In the case of the semiconductor memory, a control input of each CSL switch is connected to an AND element, which ANDs the CSL signal with the MDQ/LDQ switch signal and thereby activates the CSL switches only in cell blocks in which a word line has been activated.

Integrated semiconductor memory circuit and a method for operating the same

An integrated semiconductor memory, and method for operating such a memory, in particular a DRAM memory, having local data lines (LDQT, LDQC) segmented in the column direction (Y), which local data lines can be connected by a CSL switch in response to a column select signal fed via a CSL line (CSL) running in the row direction (X) to primary sense amplifiers for transferring or accepting spread data signals to or from bit lines of the respective segment (I, II, III), LDQ switches are arranged at the interfaces between adjacent segments of the local data lines (LDQT, LDQC) for their connection to the local data lines (LDQT, LDQC) of adjacent segments (I, II, III). LDQ switches, depending on a control signal fed separately to each of said LDQ switches, are closed during a precharge phase, which takes place before each read cycle, of at least two adjacent LDQ segments.

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Munich, Germany

Joerg Kliewer