Texas Instruments Corporation

Texas Instruments Incorporated Deutschland, Gmbh

Joerg Kirchner

Stefan Dietrich

Ivan Shumkov

Erich Bayer

Michael Lueders

Kevin Scoones

Ruediger Ganz

Christian Harder

Neil Gibson

Nicola Rasera

Gaetano Maria Walter Petrina

Martin Priess

Stefan Schimonsky

Michael Couleur

Stefan Herzer

Antonio Priego

Erich-Johann Bayer

Carsten Stoerk

Eduardas Jodka

Julian Becker

Thomas Keller

Hermann Seibold

Ivo Huber

Gaetano Petrina

Christian Schimpfle

Florian Neveu

The techniques and circuits, described herein, include solutions for pass-through operation including overcurrent protection in buck-boost converters. In some aspects, first and second switches selectively couple inputs of a peak current comparator to inputs of an error amplifier during pass-through operation. As part of peak current control scheme, one of the peak current comparator inputs is coupled to a current sensor that senses a current through an inductor of the buck-boost converter. As a result, an output of the error amplifier tracks the inductor current during pass-through mode, which may be utilized to implement inductor overcurrent protection in the pass-through mode.

DC-DC converter topology with switching overcurrent protection

A soft-start circuit includes an error amplifier, a reference voltage ramp circuit, and a minimum current clamp circuit. The error amplifier is configured to generate a difference voltage representing a difference of a feedback voltage and a reference voltage ramp. The reference voltage ramp circuit is configured to generate the reference voltage ramp. The minimum current clamp circuit is configured to clamp an output of the error amplifier to a predetermined minimum voltage.

Self-adjusting DC/DC converter soft-start mechanism

To facilitate current sensing for valley current-controlled power converters, an example apparatus includes a comparator having a first terminal, a second terminal, and an output. A first transistor has a first drain coupled to the first terminal of the comparator. A second transistor has a second drain coupled to the first terminal of the comparator. A third transistor has a third drain coupled to the second terminal of the comparator.

Current sensing for valley current-controlled power converters

Aspects of the present disclosure provide for a circuit. In at least some examples, the circuit includes a first switch coupled between a first node and a second node and a second switch coupled between a third node and the second node. The circuit further includes a resistor coupled between the second node and a fourth node and a capacitor comprising a first terminal coupled to the fourth node and a second terminal. The circuit further includes a transistor comprising a drain terminal coupled to the third node, a source terminal coupled to a fifth node, and a gate terminal and an amplifier comprising a first input terminal coupled to the fifth node, a second input terminal coupled to the fourth node, and an output terminal coupled to a sixth node.

Current sense circuit topology

Aspects of the disclosure provide for a circuit comprising a power converter controller. In an example, the power converter controller is configured to receive a signal representative of a current of a power converter, compare the signal representative of the current of the power converter to an error signal and generate a peak current detection signal having an asserted value when the signal representative of the current of the power converter is not less than the error signal. A state machine circuit is coupled the peak current detection circuit. The state machine circuit is configured to receive the peak current detection signal, a clock signal, and a timer signal and implement a state machine to generate at least one control signal for controlling a mode and a phase of operation of the power converter based on values of the peak current detection signal, the clock signal, and the timer signal.

Switched mode power supply control topology

Methods, systems, and apparatus to facilitate current sensing for valley current-controlled power converters are disclosed. An example apparatus includes a comparator including a first terminal, a second terminal, and an output. The apparatus further includes a first transistor including a first drain coupled to the first terminal of the comparator. The apparatus further includes a second transistor including a second drain coupled to the first terminal of the comparator. The apparatus further includes a third transistor including a third drain coupled to the second terminal of the comparator.

Methods, apparatus, and systems for current sensing in valley current-controlled boost converters

A power supply system can include at least one power switch to generate an output current based on an input voltage in response to a switching signal to generate an output voltage. A feedback system generates a feedback current based on the output voltage. A mode detector generates a control current associated with the output current based on the feedback current and selects between a pulse-width modulation (PWM) mode and a pulse mode based on an amplitude of the control current. The PWM mode is associated with a sequential on-time and off-time of the at least one power switch, and the pulse mode is associated with adding an idle time between the on-time and the off-time of the at least one power switch based on the switching signal. A gate driver system generates the switching signal based on the mode.

Power supply system with pulse mode operation

A DC/DC switching converter includes high-side and low-side power NFETs coupled in series between a first pin for coupling to a first supply voltage and a second pin for coupling to a second supply voltage. A switch-node is coupled to a third pin. A first gate driver is coupled to drive a gate voltage on the high-side power NFET at a first rate and a second gate driver is coupled to drive the gate voltage of the high-side power NFET at a second rate that is higher than the first rate. A comparator is coupled to the first pin and to the gate of the high-side power NFET and further coupled to turn on the second gate driver when a gate voltage of the high-side power NFET is equal to the first supply voltage coupled to the first pin plus a threshold voltage of the high-side power NFET.

Gate voltage plateau completion circuit for DC/DC switching converters

Disclosed examples include inverting buck-boost DC-DC converter circuits with a switching circuit to alternate between first and second buck mode phases for buck operation in a first mode, including connecting an inductor and a capacitor in series between an input node and a reference node to charge the inductor and the capacitor in the first buck mode phase, and connecting the inductor and the capacitor in parallel between an output node and the reference node to discharge the inductor and the capacitor to the output node. For boost operation in a second mode, the switching circuit alternates between connecting the inductor and the capacitor in series between the input node and the reference node to discharge the inductor and charge the capacitor in a first boost mode phase, and connecting the inductor between the input node and the reference node to charge the inductor and connecting the capacitor between the first output node and the reference node to discharge the capacitor to deliver power to the output node in a second boost mode phase.

Buck-boost DC-DC converter

A current measurement linearization circuit for a DC/DC boost converter includes a back-gate sensing transistor and a back-gate reset transistor. The back-gate sensing transistor has a first terminal coupled to a first body contact of a high-side power transistor and a second terminal coupled to a second body contact of a first replica transistor in a valley-current sensing circuit. The back-gate reset transistor has a first terminal coupled to a max reference voltage that is equal to the greater of an input voltage and an output voltage and a second terminal coupled to the second body contact.

Down-mode valley-current-sense replica linearization

A timer for creating a stable on time. The timer may have a reference voltage source, and an input voltage source. The voltage sources providing voltage that can be applied to a various circuit components such as capacitors, inductors, resistors, diodes, transistors, or other components. The reference voltage source may also be modified by a set of transistors coupled as a diode before being seen by an input of a timer comparator. The reference and input voltage source signals, which may be modified by circuit components, are compared by the timer comparator and then output as a timer control signal. The timer control signal may control a voltage converter, or the switches of a voltage converter.

Timer for creating a stable on time

A controller for a DC-DC converter includes a state machine and a plurality of drivers for controlling switches in the DC-DC converter, where each state in the state machine determines a state of the drivers, and a plurality of timers, where each state in the state machine, other than a passive state, has an associated timer for the state of the drivers.

Buck-boost converter controller

Methods and apparatus for operating a DC-to-DC voltage converter that has a power stage that includes at least one switching transistor. The output voltage of the DC-to-DC voltage converter is monitored. If the output voltage drops below a lower output voltage threshold, a series of drive pulses is provided to the at least one switching transistor to commence switching of the at least one switching transistor. If the output voltage rises above an upper output voltage threshold, a random number of additional drive pulses is provided to the at least one switching transistor and then the provision of drive pulses to the at least one switching transistor is ceased.

Implementation of spread spectrum in PFM mode for DC-DC converters

A DCDC converter includes a controller, an up/down counter, a first power stage and a second power stage. The controller generates an up/down control signal. The up/down counter generates a first power stage control signal and a second power stage control signal based on the up/down control signal. The first power stage generates a first output current at a first phase and at a first voltage based on the first power stage control signal. The second power stage generates a second output current at a second phase based on the second power stage control signal. The up/down counter modifies the first power stage control signal to control the first power stage such that the first output current attenuates from a first power stage output to a secondary first power stage output. The controller can further output a control signal to modify the first voltage of the first power stage.

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Mauern, Germany

Joerg Kirchner