Nec Corporation

Nec Laboratories America, Inc.

Joerg Henkel

Haris Lekatsas

Venkata S Jakkula

Srimat T Chakradhar

An architecture for content-aware compression and/or encryption of various segments of a application is disclosed. The architecture advantageously allows decompression and decryption units to be placed various levels of a memory hierarchy.

Dynamic content-aware memory compression and encryption architecture

An embedded systems architecture is disclosed which can flexibly handle compression of both instruction code and data.

Compressed memory architecture for embedded systems

Code compression is known as an effective technique to reduce instruction memory size on an embedded system. However, code compression can also be very effective in increasing the processor-to-memory bandwidth and hence provide increased system performance. A code decompression engine having plurality of dictionary tables, coupled with decoding circuitry and appropriate control circuitry, is coupled between the processor core and the instruction cache. The code decompression engine provides one-cycle decompression of compressed instructions that are intermixed with uncompressed instructions, thereby increasing processor-to-memory bandwidth and avoiding processor stalls.

Apparatus for one-cycle decompression of compressed data and methods of operation thereof

A novel power minimizing hardware/software co-design approach is presented that partitions an embedded application into an application specific core and a software program that executes on a microprocessor core. As opposed to prior art approaches, the present approach is very comprehensive since it takes into consideration a whole embedded system. In addition, it partitions at the cost of a very small additional hardware effort. The experimental results show high energy savings while maintaining (or even slightly increasing) the performance of the initial design.

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Exton, PA, United States of America

Joerg Henkel