International Business Machines Corporation

Globalfoundries Inc.

Joerg H Walter

Matthias Klein

Norbert Hagspiel

Sascha Junghans

Joerg Deutschle

Ernst-Dieter Weissenberger

Ursel Hahn

Nils Haustein

Tim Uwe Scheideler

Dominic Mueller-Wicke

Gerrit Koch

Norbert Schumacher

Carsten Greiner

Volker Urban

Lothar Felten

Minh Cuong Tran

Andre Gaschler

Juergen Koehl

Christopher S Smith

Juergen Saalmueller

Ulrike Schmidt

Walter Pietschmann

Marcel Naggatz

Harald Gerst

Generating instructions, in particular for mailbox verification in a simulation environment. A sequence of instructions is received, as well as selection data representative of a plurality of commands including a special command. Repeatedly selecting one of the plurality of commands and outputting an instruction based on the selected command. The outputting of an instruction includes outputting a next instruction in the sequence of instructions if the selected command is the special command, and outputting an instruction associated with the command if the selected command is not the special command.

Instruction generation based on selection or non-selection of a special command

A data processing apparatus includes a number of processor cores, a shared processor cache, a bus unit and a bus controller. The shared processor cache is connected to each of the processor cores and to a main memory. The bus unit is connected to the shared processor cache by a bus controller for transferring data to/from an I/O device. In order to achieve further improvements to the data transfer rate between the processor cache and I/O devices, the bus controller is configured, in response to receiving a descriptor from a processor core, to perform a direct memory access to the shared processor cache for transferring data according to the descriptor from the shared processor cache to the I/O device via the bus unit.

Data transfer using a descriptor

It is determined, if a simulated hardware signal of a design for an electronic circuit has an influence on a checker for simulation errors. To achieve this, a checker control flow database is generated for a static code description containing checkers and concerned simulated signals. Further, a database based on the output of instrumented verification code is generated, thus gaining dynamic information about the verification code. Herein, the hardware signal values will be associated with colored values or, alternatively, attributed values. For the checkers in the checker control flow database, a list of attributes is generated and stored. Based on the above operations, a hardware signal database is generated, wherein hardware signals are mapped to a list of checkers, based on determining, for each checker in the checker database, the associated hardware signals from its list of attributed values.

Ensuring completeness of interface signal checking in functional verification

Automatically configuring backup client systems and backup server systems in a backup environment includes the following steps: determining if a new backup client system is available in the backup environment; in case of an available new backup client system a backup configuration module performs the sub-steps of: determining data types the new backup client system has to backup; determining corresponding backup policies for the determined data types based on a backup policy table mapping data types with backup policies; selecting a backup server system for the determined data types based on a backup server table including connection details of available backup server systems; configuring the determined backup policies for the data types of the new backup client system on the selected backup server systems; and updating the backup server table with an identifier of the new backup client system and an identifier of the backup policy.

Method for automatically configuring backup client systems and backup server systems in a backup environment

According to embodiments of the invention, methods, computer system, and apparatus for virtual channel management and bus multiplexing are disclosed. The method may include establishing a virtual channel from a first device to a second device via a bus, the bus having a first bus capacity and a second bus capacity, the second bus capacity having greater capacity than the first bus capacity, determining whether a store command is issued for the first bus capacity, determining whether the first bus capacity is available, and allocating the second bus capacity and marking the second bus capacity as unavailable in response to the store command if the first bus capacity is unavailable.

Resource allocation by virtual channel management and bus multiplexing

Instruction output dependent on a random number-based selection or non-selection of a special command from a group of commands

A data processing system is provided which includes a processor nest communicatively coupled to an input/output bus by a bus controller, and a service interface controller communicatively coupled to the processor nest. The system includes storage for storing commands for the bus controller and associated command data and resulting status data, the storage being communicatively coupled to the processor nest and the bus controller. The service interface controller is configured, in response to received service commands, to read and write the storage, to execute the command specified in the storage, to retrieve the result of the command, and to store the result in the storage.

Initializing I/O devices

An apparatus for tracing data from a data bus in a first clock domain operating at a first clock frequency to a trace array in a second clock domain operating at a second clock frequency, wherein the first clock frequency is lower than the second clock frequency. The apparatus includes a change detector to detect a change of the data on the data bus in the first clock domain, a trigger responsive to the change detector to send a trigger pulse to the second clock domain, pulse synchronization on the second clock domain responsive to the trigger pulse to synchronize the trigger pulse to the second clock frequency of the second clock domain by a meta-stability latch, as well as a data capture in the second clock domain responsive to the pulse synchronization to capture data from the data bus and to store the captured data in the trace array.

Tracing data from an asynchronous interface

A method of avoiding a write collision in single port memory devices from two independent write operations is described. A first data object from a first write operation is divided into a first even sub-data object and first odd sub-data object. A second data object from a second write operation is divided into a second even sub-data object and a second odd sub-data object. The first even sub-data object is stored to a first single port memory device and the second odd sub-data object to a second single port memory device when the first write operation and the second write operation occur at the same time. The second even sub-data object is stored to the first single port memory device and the first odd sub-data object to the second single port memory device when the first write operation and the second write operation occur at the same time.

Write and read collision avoidance in single port memory devices

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Stuttgart, Germany

Joerg H Walter