Texas Instruments Incorporated Deutschland, Gmbh

Texas Instruments Corporation

Joerg Erik Goller

Norbert Reichel

Erich Bayer

Antonio Priego

Thomas Keller

Harald Sandner

An integrated circuit. The integrated circuit comprises a timebase generator and a switch mode direct current-to-direct current (DC-to-DC) voltage converter coupled to the timebase generator. The timebase generator comprises a first linear feedback shift register (LFSR), a signal generator having an input coupled to an output of the first LFSR; and a digital divider comprising a second LFSR and a programmable digital divider, wherein a clock input of the programmable digital divider is coupled to an output of the signal generator, wherein an output of the programmable digital divider is coupled to a clock input of the first LFSR and is coupled to a clock input of the second LFSR, and wherein an output of the second LFSR is coupled to a program input of the programmable digital divider.

Reduction of low frequency noise in a discrete spread spectrum timebase

An integrated circuit. The integrated circuit comprises a timebase generator and a switch mode direct current-to-direct current (DC-to-DC) converter coupled to the timebase generator. The timebase generator comprises a linear feedback shift register (LFSR) having an output and a logic circuit comprising a first logic inverter, a first AND logic gate, and a first multiplexer, wherein the first logic inverter has an input coupled to a most significant bit of the output of the LFSR, wherein the first AND logic gate has a first input coupled to a second most significant bit of the output of the LFSR and a second input coupled to an output of the first logic inverter, wherein a selector input of the first multiplexer is coupled to an output of the first AND logic gate.

Spectral shaping of spread spectrum clocks/frequencies through post processing

A device for generating clock signals for use with a plurality of DDR memory devices on a dual in-line memory module (DIMM) board is provided that has a data buffer for buffering data. A clock divider divides a first clock signal (CLK) having a first clock frequency to generate a second clock signal (CLK) having a second clock frequency which is an integer multiple of the first clock frequency. A shift register (SH) receives the second clock signal as a data input signal, and comprises a plurality flip-flops having clock inputs coupled to receive the first clock signal (CLK), and further coupled so that the data output of a preceding flip-flop is coupled to be the data input of a following flip-flop. The second clock signal is shifted through the shift register (SH) in response to the first clock signal (CLK) to generate a plurality of shifted clock signals (CLK. . . , CLK) at respective data outputs of the plurality of flip-flops. A multiplexer commonly coupled to the data outputs of the flip-flops selects one of the shifted clock signals (CLK. . . , CLK) to serve as an output clock signal for transmission of the buffered data to a memory device.

Integrated circuit for clock generation for memory devices

A power supply unit includes a boost converter having an input node and output node. The output node is coupled to a high-side of an H-bridge that is for supplying power to a capacitive load that is coupled to a first node and to a second node of the H-bridge. A first diode is coupled in forward direction between the first node of the H-bridge and the input node of the boost converter. A second diode is coupled in forward direction between the second node of the H-bridge and the input node of the boost converter.

Power supply unit and a method for operating the same

A device for generating clock signals for use with a plurality of DDR memory devices on a dual in-line memory module (DIMM) board is provided that has a data buffer for buffering data. A clock divider divides a first clock signal (CLK) having a first clock frequency to generate a second clock signal (CLK) having a second clock frequency which is an integer multiple of the first clock frequency. A shift register (SH) receives the second clock signal as a data input signal, and comprises a plurality flip-flops having clock inputs coupled to receive the first clock signal (CLK), and further coupled so that the data output of a preceding flip-flop is coupled to be the data input of a following flip-flop. The second clock signal is shifted through the shift register (SH) in response to the first clock signal (CLK) to generate a plurality of shifted clock signals (CLKCLK) at respective data outputs of the plurality of flip-flops. A multiplexer commonly coupled to the data outputs of the flip-flops selects one of the shifted clock signals (CLKCLK) to serve as an output clock signal for transmission of the buffered data to a memory device.

A device for generating clock signals for use with a plurality of DDR memory devices on a dual in-line memory module (DIMM) board is provided that has a data buffer for buffering data. A clock divider divides a first clock signal (CLK) having a first clock frequency to generate a second clock signal (CLK) having a second clock frequency which is an integer multiple of the first clock frequency. A shift register (SH) receives the second clock signal as a data input signal, and comprises a plurality flip-flops having clock inputs coupled to receive the first clock signal (CLK), and further coupled so that the data output of a preceding flip-flop is coupled to be the data input of a following flip-flop. The second clock signal is shifted through the shift register (SH) in response to the first clock signal (CLK) to generate a plurality of shifted clock signals (CLK, . . . , CLK) at respective data outputs of the plurality of flip-flops. A multiplexer commonly coupled to the data outputs of the flip-flops selects one of the shifted clock signals (CLK, . . . , CLK) to serve as an output clock signal for transmission of the buffered data to a memory device.

The present invention relates to an electronic transmitter for serially transmitting bit sequences. The electronic transmitter includes a detection deviceand a transmitting deviceThe detection deviceis adapted to detect a predefined bit sequence for transmittal. The predefined bit sequence is susceptible to inter-symbol-interference. The transmitting deviceis adapted to transmit serially the detected predefined bit sequence in such a way, that a duration for transmittal of a particular bit in said predefined bit sequence is longer than a duration of transmittal of remaining bits in said predefined bit sequence.

Method of transmitting serial bit-stream and electronic transmitter for transmitting a serial bit-stream

Digital data are recovered from a clocked serial input signal. The input signal is sampled with a sampling clock signal supplied by a first phase interpolator to obtain a sampled digital signal. The first phase interpolator is controlled with a voting circuit to adjust the phase of the sampling clock relative to the eye in the eye-diagram of the input signal. The first phase interpolator has signal inputs connected to signal outputs of a voltage controlled oscillator in a phase-locked loop circuit that has a reference signal input to which the reference clock signal is applied. The sampled digital signal is written to a single-bit FIFO buffer with a write clock signal that has the same timing as the sampling clock. A filtered output signal is read from the FIFO buffer with a read clock signal supplied by a second phase interpolator that has signal inputs connected to the signal outputs of the voltage controlled oscillator in the phase-locked loop. The second phase interpolator is controlled with a pointer monitor that monitors the write and read select pointers in the FIFO buffer to adjust the timing of the read clock signal relative to the write clock signal. With this method, the hunting jitter is filtered out while a frequency offset is still allowed between the reference clock and the data signal.

Method of recovering digital data from a clocked serial input signal and clocked data recovery circuit

A data synchronization arrangement is provided for exchanging clocked data between different clock domains running at the same clock frequency but at an arbitrary relative phase shift. An input data stream synchronized in the first clock domain is written into respective locations of a buffer memory through a write select multiplexer under control of a write select shift register clocked by the first domain clock. An output data stream synchronized in the second clock domain is read from the respective locations of the buffer memory through a real select multiplexer under control of a read select shift register clocked by the second domain clock. A bit synchronization circuit is provided for loading the read select shift register with a bit pattern that has a relative offset relative to the bit pattern of the write select shift register, to correlate for the difference in clock phases.

Data synchronization arrangement

A data synchronization arrangement is provided that is fail-safe at high speed and low power consumption, for exchanging clocked data between different clock domains running in a digital processing equipment at the same clock frequency but at an arbitrary relative phase shift. A register arrangement has a predetermined number of parallel registers, each register having a data input, a write clock input, a read clock input and a data output. A write select multiplexer has an input receiving a write clock signal from a first clock domain, one clock output for each of the parallel registers and connected to a write clock input of a respective register, and one write select input for each clock output. A read select multiplexer has an input receiving a read clock signal from a second clock domain, one clock output for each of the parallel registers and connected to a read clock input of a respective register, and one read select input for each clock output. A write select shift register has a number of stages corresponding to the predetermined number of registers and an output stage looped back to an input stage.

A system and method is disclosed for a fast locking (e.g., within 1.5 sync bit times or the first data transition) clock and data recovery (CDR) system used in high speed data communications applications (e.g., ASIC and microprocessor chips). The CDR circuit takes multiple (e.g., 8) phases of the local clock, which are offset (e.g., by 45 degrees), and uses the multiple phases to latch the state of data at multiple times, and uses the latched data to determine which of the multiple phases captured a data transition. The CDR circuit compares the indicated phase to the phase used to capture a previous data transition and uses such information to, produce a stable selection of a clock phase. The selected clock phase is then employed to provide a recovered clock and data signals (CLK_OUT, and DATA_OUT), in association with the incoming serial data stream independent of jitter and free of metastable conditions.

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Tiefenbach, Germany

Joerg Erik Goller