Freescale Semiconductor,inc.

USA As Represented by Secretary of the Navy

Ionq, Inc.

Worldcom, Inc.

Joel Zvi Apisdorf

William Shvodian

Sam Brandon Sandbote

Matthew L Welborn

Jason Madjdi Amini

James Michael Williams

Phillip Douglas Solomon

Michael Daniel Poole

John W McCorkle

Timothy R Miller

Jack B Dennis

Knut T Odman

Sergio T Montano

Russell G Dowe

Keith Burden

The disclosure describes various aspects of a system with scalable and programmable coherent waveform generators. A network and digital-to-analog conversion (DAC) cards used by the network are described where each DAC card has a clock divider/replicator device with an input SYNC pin, a digital logic component, and one or more DAC components, and each output of the DAC components is used to control optical beams for a separate qubit of a quantum information processing (QIP) system. The network also includes a first distribution network to provide a clock signal to the clock divider/replicator device in the DAC cards, and a second distribution network to provide a start signal to the DAC cards, where the start signal is used by the digital logic component in the DAC card to assert the input SYNC pin when the start signal is asserted unless it is masked by the digital logic component.

Scalable and programmable coherent waveform generators

A system and method process data elements with instruction-level parallelism. An instruction buffer holds a first instruction and a second instruction, the first instruction being associated with a first thread, and the second instruction being associated with a second thread. A dependency counter counts satisfaction of dependencies of instructions of the second thread on instructions of the first thread. An instruction control unit is coupled to the instruction buffer and the dependency counter, the instruction control unit increments and decrements the dependency counter according to dependency information included in instructions. An execution switch is coupled to the instruction control unit and the instruction buffer, and the execution switch routes instructions to instruction execution units.

System and method for instruction-level parallelism in a programmable multiple network processor environment

A system and method forward data between processing elements. A first processing element includes an address register that stores a first memory address. A forwarding storage element is coupled to the first processing element. A second processing element, coupled to the forwarding storage element, transmits a second memory address to the forwarding storage element. The forwarding storage transmits the second memory address to the first processing element, and the first processing element compares the second memory address with the first memory address.

System and method for data forwarding in a programmable multiple network processor environment

A method () is provided of operating a local transceiver (), comprising: setting the local transceiver into an operational mode; operating the local transceiver in a polling mode (); receiving a quiescent begin indicator identifying a beginning of a quiescent mode (); setting a portion of the local transceiver into a low power consumption mode in response to the quiescent begin indicator (); measuring an elapsed time since receiving the quiescent begin indicator as a quiescent time (); and returning the portion of the local transceiver to the operational mode based on a quiescent end indicator).

System and method for operating a communications system

A method is provided for transmitting data. A first device generates a first signal having a first duty cycle, comprising a first gated-on portion and a first gated-off portion in a time slot; and a second device generates a second signal having second duty cycle, comprising a second gated-on portion and a second gated-off portion in the same time slot. The first gated-on portion is generated during a first segment of the time slot and the first gated-off portion is generated during a second segment of the time slot, while the second gated-on portion is generated during the second segment and the second gated-off portion is generated during the first segment. Media access control (MAC) can be used to further define positions within time slots and provide error correction, power control, and the like. A preamble can be transmitted at an increased power level to facilitate acquisition.

Method for sharing bandwidth using reduced duty cycle signals and media access control

A network bridge () is provided, comprising: a local interface () configured to transmit and receive local signals in a local network (); a bridging interface () configured to transmit and receive bridging signals in a bridging network (); a control circuit () configured to pass outgoing local data packets from the local network to the bridging network and to pass incoming bridging payloads from the bridging network to the local network; and an address translation circuit () configured to provide the control circuit with address translation data identifying a correspondence between local packet addresses and global packet addresses. The control circuit translates outgoing local addresses to outgoing global addresses (), and the control circuit translates incoming global addresses to incoming local addresses (), based on the address translation data.

System and method for translucent bridging

A method is provided for operating a transceiver that comprises: transmitting a preamble; transmitting an outer header identifying parameters of an outer payload, after transmitting the preamble; and transmitting the outer payload after transmitting the outer header. The transmitting of the outer payload includes: transmitting an inner header identifying parameters of an inner payload; transmitting an inner payload after transmitting the inner header; and repeating the transmitting of the inner header and the transmitting of the inner payload a plurality of times. A corresponding method of operating a receiver functions by receiving each of these transmitted elements.

Method of transmitting and receiving data

A method is provided for a remote device to monitor and communicate with a wireless network using cyclic beacons. The remote device receives a beacon, which beacon includes beacon information that defines a superframe. From the beacon information, the remote device determines whether the received beacon and the associated superframe are assigned to a network device or are unassigned. By receiving as many beacons as there are allowable devices in the network, the remote device can determine if the network is full. If the remote device runs through all of the beacons and all indicate that their associated superframes are assigned, then the remote device determines that the network is full and performs a network-full function. If the remote device receives a beacon that indicates that its associated superframe is unassigned, it determines that the network is not full and performs an association request during the unassigned superframe.

Method of operating a media access controller

A system and method process data elements on multiple processing elements. A first processing element processes a task. A second processing element, coupled to the first processing element, is associated with a task. The first processing element sends a critical-section end signal to the second processing element while processing the task at the first processing element. The second processing element resumes the task in response to receiving the critical-section end signal.

System and method for processing overlapping tasks in a programmable network processor environment

A system and method for checking for data transmission errors in a network includes a cyclic redundancy code (CRC) generator and a processing device. The CRC generator receives a stream of data representing cells in a packet of data. The CRC generator generates a CRC value for each cell and transmits the CRC value to a processing device. The processing device combines the cell CRC values to generate a CRC for a packet of data. The processing device then compares the packet CRC to an expected value to determine whether an error occurred in the data transmission.

Growing community of inventors

Reston, VA, United States of America

Joel Zvi Apisdorf