Arm Limited

Advanced Micro Devices Corporation

Joel Thornton Irby

Mudit Bhargava

Grady L Giles

Saurabh Pijuskumar Sinha

Yew Keong Chong

George McNeil Lattimore

Andy Wangkun Chen

Vikas Chandra

Russell J Schreiber

Rahul Mathur

Supreet Jeloka

Xiaoqing Xu

Wendy Arnott Elsasser

James Dennis Dodrill

Carl Wayne Vineyard

Joshua Randall

Floyd L Dankert

Alan Jeremy Becker

Karthik Natarajan

Srinivasan Srinath

Carl D Dietz

Sudha Thiruvengadam

Gregory A Constant

Alexander W Schaefer

Amy M Novak

Sudhir S Kudva

An integrated circuit includes a latch array including a plurality of latches logically configured in rows and columns, a plurality of repair latches operatively coupled to the plurality of latches and latch array built in self-test and repair logic (LABISTRL) coupled to the plurality of latches. In some implementations the LABISTRL configures latches in the array as one or more column serial test shift register, detects one or more defective latches of the plurality of latches based on applied test data, and selects at least one repair latch in response to detection of at least one defective latch.

Repairable latch array

Various implementations described herein refer to a method for tracking abnormal incidents while monitoring activity of logic circuitry. The method may include detecting a tamper event related to the abnormal incidents and storing an attack signature related to the tamper event. The attack signature may be stored in non-volatile memory (NVM), such as, e.g., correlated electron random access memory (CeRAM).

Tamper detection and response techniques

A system-on-chip is provided that includes functional circuitry that performs a function. Control circuitry controls the function based one or more configuration parameters. Non-volatile storage circuitry includes a plurality of non-volatile storage cells each being adapted to write at least a bit of the one or more configuration parameters in a rewritable, persistent manner a plurality of times. Read circuitry locally accesses the non-volatile storage circuitry, obtains the one or more configuration parameters from the non-volatile storage circuitry and provides the one or more configuration parameters to the control circuitry. Write circuitry obtains the one or more configuration parameters and provides the one or more configuration parameters to the non-volatile storage circuitry by locally accessing the non-volatile storage circuitry.

Non-volatile memory on chip

A three-dimensional (3D) storage circuit includes two or more tiers of semiconductor dies, and a storage array of bitcells distributed on the two or more tiers to form a plurality of storage subarrays. One of the storage subarrays is arranged on a respective one of the tiers. Row and column replica/dummy tracking cells are arranged on each of the tiers. A timing circuit is coupled to the tracking cells of each of the tiers. In response to receipt of tier-specific trim bits for each of the tiers, the timing circuit independently controls a timing and/or voltage state of each of the tiers during an access operation of the 3D storage circuit to account for process and/or thermal variation between tiers of the 3D storage circuit.

3D storage architecture with tier-specific controls

A three-dimensional (3D) integrated circuit (IC) can include a bottom tier with first circuitry and first backside TSVs coupled to a substrate; a top tier coupled to the first tier at a front side and having second circuitry and second backside TSVs; and a heat conductor on the second backside TSVs of the top tier. The heat conductor is coupled to the second backside TSVs to provide improved heat dissipation through the top tier. During pre-bond testing, the top tier can be tested at speed using the second backside TSVs.

Three-dimensional integrated circuit test and improved thermal dissipation

A multi-die integrated circuit with improved testability can include at least two dies that combined comprise an integrated circuit for a self-contained system, which includes logic and design-for-test features. The integrated circuit is split into at least two portions, where each portion is disposed on a corresponding one of the at least two dies. As part of the improved testability for both pre-bond testing of logic and post-bond testing of inter-die connections, at least one of the at least two dies further comprises a split-circuit-boundary scan chain. An automated design tool can be used to determine optimal ways for the integrated circuit for a self-contained system to be split into at least two portions for the corresponding at least two dies. In addition, a split-circuit-boundary scan chain option can be applied for each portion, via the automated design tool, to ensure boundary scans are available on timing paths.

Multi-die integrated circuits with improved testability

A method and apparatus is provided for wear leveling of a storage medium in an electronic device. Wear leveling is achieved by mapping each logical memory address to a corresponding physical memory address. The mapping information is consistent over an on-period of a power cycle, but changes from one power cycle to another. The mapping information, such as a key value for example, may be stored in non-volatile memory such as, for example, a correlated electron random switch (CES) storage element. The mapping may be obtained by manipulating bits of the logical address to obtain the physical address.

Method and apparatus for memory wear leveling

Disclosed are methods, systems and devices for operation of memory device. In one aspect, bit positions of a portion of a memory array may be placed in a first value state. Values to be written to the bit positions may be determined subsequent to placement of the bit positions in the first value state. Values at selected ones of the bit positions may then be changed from the first value state to a second value state while maintaining remaining unselected ones of the bit positions in the first value state so that the bit positions store or represent the values determined to be written to the bit positions.

Method, system and device for memory device operation

An apparatus is provided for testing storage elements that include a variable impedance element switchable between a first impedance state and a second impedance state. The apparatus includes an interconnect circuit for coupling storage elements in a selected arrangement. The apparatus includes an impedance sensing circuit operable to measure at least a resistive component of an impedance of the coupled storage elements and a test controller operable to configure the interconnect circuit and initiate measurement of the combined impedance of the coupled storage elements by the impedance sensing circuit. The impedance sensing circuit compares the measured impedance with at least a resistive component of an expected impedance. The storage elements and apparatus may form part of an integrated circuit. A storage element may include a correlated electron switch, for example.

Fast quasi-parity checker for correlated electron switch (CES) memory array

A power grid provides power to one or more modules of an integrated circuit device via a virtual power supply signal. A test module is configured to respond to assertion of a test signal so that, when the power grid is working properly and is not power gated, an output of the test module matches the virtual power supply. When the power grid is not working properly, the output of the test module is a fixed logic signal that does not vary based on the power gated state of the one or more modules.

Techniques and circuits for testing a virtual power supply at an integrated circuit device

An integrated circuit is provided for self-repair of a memory array. The circuit includes first word lines coupled to first memory rows of the memory array, one first word line for each bit of a line address word, second word lines coupled to one or more spare memory rows of the memory array. Repair configuration data is stored in memory cells within the integrated circuit to direct memory accesses to spare memory rows rather than dysfunctional first memory rows. A memory cell may be based on a correlated electron switch (CES). A built-in self-test circuit is provided to facilitate setting of repair configuration data. The repair data may be reconfigurable, enabling operating margins to be improved by testing under various operating conditions.

Fast memory array repair using local correlated electron switch (CES) memory cells

A content addressable memory (CAM) of a data processing device can operate in a normal mode or a test mode. In the normal mode, the CAM provides a match value in response to determining that a received data value matches one of a plurality of values stored at memory locations of the CAM. In a test mode of operation, a plurality of test signals are applied to the CAM, and the CAM provides a match value in response to assertion of one of the test signals. The match value is applied to a functional module associated with the CAM to determine a test result. Accordingly, the test signals applied to the CAM provide a flexible way to generate match values and apply those values to the functional module during testing of the data processing device.

Content addressable memory match signal test device and methods thereof

An integrated circuit. The integrated circuit includes a plurality of logic circuits. The integrated circuit further includes a scan chain including a plurality of scan elements coupled in series, wherein the scan chain is configured to load stimulus data to be applied to the logic circuits for testing. The scan chain is further configured to capture data subsequent to applying the stimulus data. The integrated circuit also includes an embedded memory having a read port, wherein the read port is coupled to one or more of the plurality of logic circuits via a read path. The embedded memory includes a virtual entry having a plurality of scan-controllable storage elements. During testing, the virtual entry is operable to apply transition data to the read path in order to cause logic state transitions in the one or more logic circuits in the read path.

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Austin, TX, United States of America

Joel Thornton Irby