International Business Machines Corporation

Joel T Ficke

James David Strom

Grant Paul Kesselring

David Michael Friend

Jianguo Yao

Kennedy K Cheruiyot

Terence B Hook

William Eric Hall

Michael Sperling

Larry Wissel

Andrew Douglas Davies

Erik S Unterborn

A circuit for implementing a control voltage mirror is provided. A filter includes a filter capacitor connected to a control voltage and a distal side of the capacitor connected to a voltage reference. The control voltage mirror includes an operational amplifier having a positive input connected to the control voltage, and a negative input is connected to an output and coupled to the distal side of the capacitor. Voltage across the capacitor is held to be near or at zero volts, substantially eliminating capacitor leakage current.

Control voltage mirror circuit

A variable frequency oscillator device includes a first inverter stage that is designed to invert an input signal to generate a sawtooth signal by charging and discharging a capacitor using current sources that each provides a respective amount of current that is responsive to a control signal and to a dampening signal. A second inverter stage is designed to generate a first inverted signal from the sawtooth signal of the first inverter stage. A third inverter stage is designed to generate a second inverted signal from the first inverted signal, and dampen a signal transition rate for the first inverted signal based upon the control signal.

Variable frequency oscillator with specialized inverter stages

A semiconductor chip having a P&#x2212; substrate and an N+ epitaxial layer grown on the P&#x2212; substrate is shown. A P&#x2212; circuit layer is grown on top of the N+ epitaxial layer. A first moat having an electrically quiet ground connected to a first N+ epitaxial region is created by isolating the first N+ epitaxial region with a first deep trench. The first moat is surrounded, except for a DC path, by a second moat with a second N+ epitaxial region, created by isolating the second N+ epitaxial region with a second deep trench. The second moat may be arranged as a rectangular spiral around the first moat.

Moat construction to reduce noise coupling to a quiet supply

A system is disclosed, which may include a differential charge pump. The differential charge pump may include a first and a second H-bridge circuit, each driving, on a respective output, an output current that is substantially similar over an output voltage operating range. The differential charge pump may be designed to receive increment, decrement and bias signals, and drive, in response to the increment and decrement signals, the output current to draw each H-bridge circuit output towards a first or a second supply voltage. The differential charge pump may also be designed to increase, in response to the bias signals, the output voltage operating range over which the output current is substantially similar. The differential charge pump may also include a bias signal generator, designed to generate bias signals in response to H-bridge circuit output voltages.

Charge pump operating voltage range control using dynamic biasing

A method and circuit for implementing a dual speed level shifter with automatic mode control, and a design structure on which the subject circuit resides are provided. A low speed level shifter and a high speed level shifter are used to provide a wide frequency range of operation. The circuit operates in one of a low speed mode or a high speed mode. The appropriate mode is selected automatically by detecting the frequency of the signal to be level shifted. When the incoming signal is slower than a reference frequency, the low speed level shifter is selected, and when the incoming signal is faster than the reference frequency, the high speed level shifter is selected.

Implementing dual speed level shifter with automatic mode control

The present invention provides an apparatus and method for a frequency adaptive level shifter circuit. The frequency adaptive level shifter circuit includes a first inverter, a second inverter coupled to the output of the first inverter, a capacitor coupled to the output of the second inverter, and a resistor coupled to the output of the capacitor. The frequency adaptive level shifter circuit further includes a transistor coupled to the output of the resistor, wherein the transistor has a gate connected to a reference voltage, a third inverter coupled to the output of the capacitor, and a fourth inverter coupled to the output of the third inverter and the transistor and outputting the signal.

Structure for a frequency adaptive level shifter circuit

Electronic devices and methods are disclosed to provide and to test a physically unclonable function (PUF) based on relative threshold voltages of one or more pairs of transistors. In a particular embodiment, an electronic device is operable to generate a response to a challenge. The electronic device includes a plurality of transistors, with each of the plurality of transistors having a threshold voltage substantially equal to an intended threshold voltage. The electronic device includes a challenge input configured to receive the challenge. The challenge input includes one or more bits that are used to individually select each of a pair of transistors of the plurality of transistors. The electronic device also includes a comparator to receive an output voltage from each of the pair of transistors and to generate a response indicating which of the pair of transistors has the higher output voltage. The output voltage of each of the pair of transistors varies based on the threshold voltage of each of the pair of transistors.

Physically unclonable function implemented through threshold voltage comparison

A method and circuit for implementing dynamic voltage sensing and a trigger circuit, and a design structure on which the subject circuits resides are provided. The voltage sensing circuit includes a first quiet oscillator generating a reference clock, and a second noisy oscillator generating a noisy clock. A digital control loop coupled to the first quiet oscillator and the second noisy oscillator matches frequency of the first quiet oscillator and the second noisy oscillator. The reference clock drives a first predefined-bit shift register and the noisy clock drives a second predefined-bit shift register, where the second predefined-bit shift register is greater than the first predefined-bit shift register. When the first predefined-bit shift register overflows, the contents of the second predefined-bit shift register are evaluated. The contents of the second predefined-bit shift register are compared with a noise threshold select value to identify a noise event and trigger a noise detector control output.

Implementing integral dynamic voltage sensing and trigger

A screening method and circuit for implementing a Physically Unclonable Function (PUF), and a design structure on which the subject circuit resides are provided. A plurality of field effect transistors (FETs) is coupled to a low-offset dynamic comparator and is respectively selected to provide a plurality of FET pairs. For each FET pair, a voltage offset to obtain a comparator output transition is identified and recorded. The recorded voltage offset for each FET pair is compared with a margin threshold value. Each FET pair having an identified voltage offset less than the margin threshold value is discarded or disabled for PUF response generation use.

Implementing screening for single FET compare of physically unclonable function (PUF)

A method and a phase locked loop (PLL) circuit for implementing enhanced locking capability with a wide range dynamic reference clock, and a design structure on which the subject circuit resides are provided. The PLL circuit includes a Voltage Controlled Oscillator (VCO) and a plurality of filter comparators receiving a differential filter VCO control voltage. The plurality of filter comparators comparing the differential filter VCO control voltage values, provides a respective gate enable signal responsive to the compared differential filter VCO control voltage values. A clock signal is applied to an up/down counter responsive to the respective gate enable signal and the wide range dynamic reference clock. The count values of the up/down counter are provided to the VCO to select a respective frequency range for the VCO.

Growing community of inventors

Bloomer, WI, United States of America

Joel T Ficke