Rca Inc.

Joel Roy Oberman

Roger Green Stewart

Russell G Ott

A data processor system having a total memory capacity, an integrated circuit chip having thereon a central processing unit (CPU), a ROM, a RAM, a first decoder responsive to addresses supplied thereto for determining the location of the RAM in the total memory capacity, and logic for disabling the ROM from the CPU and for relocating the RAM in the total memory capacity. Also provided are a generator for generating a first control signal having first and second states, first gating logic responsive to the first state of the control signal to disable the ROM and to disconnect the output of the first decoder from the RAM. Further provided is an adjustable second decoder positioned externally of the chip and responsive to addresses supplied thereto from the CPU to generate an output signal defining a selectable location of the RAM in the total memory capacity, and second gating logic responsive to the first state of the control signal to connect the output signal of the adjustable second decoder to the RAM to thereby define the selectable location of the RAM in the total memory capacity.

Single chip microcomputer with external decoder and memory and internal

In a data processing system having a memory and employing N-bit bytes and two byte addresses, a branch instruction which can cross one page boundary is executed without having to use calculations to effect a change in the contents of the program counter (PC). It is determined whether the value V1 of the (N-1) least significant bits (LSB's ) of the lower order byte of the two byte branch address is greater or less than the value V2 of the (N-1) least significant bits (LSB's) of the lower order byte of the address to which the PC is pointing and also whether PC N.noteq.BR N where PC N and BR N are the most significant bits of the lower order bytes of the PC address and the branch address, respectively. If V1&lt;V2, PC N=1, and PC N.noteq.BR N, the upper order byte of the PC address is incremented by 1 and if V1&gt;V2, PC N=0, and PC N.noteq.BR 7, the upper order byte of the PC address is decremented by 1.

Implementation of instruction for a branch which can cross one page

The operating potential to a storage element is supplied via an impedance element connected between a source of operating potential and a first power terminal of the storage element adapted to receive an operating potential. Information is written into the storage element via a gating transistor having its conduction path connected between an input line and a data input point to the storage element. Write circuitry includes means connected between the first power terminal and the input line. During a write operation, the write circuit, while applying the desired bit of information to the cell input, causes current to flow through the impedance element lowering the potential across the flip-flop until the desired bit of information is written into the cell.

Write enhancement circuit

A memory array includes row conductors which have to be charged to a first level prior to each read-out cycle. During a read-out cycle the row conductors may or may not be discharged to a second level depending on whether a '1' or a '0' is stored at selected bit locations. The memory array also includes 'dummy' row conductors which are discharged to the second level each time the contents of the array are read out. Means are provided for charging the row conductors including the 'dummy' row conductors to the first level prior to each read-out, for sensing the charge level on the 'dummy' row conductors, and for terminating the charging cycle when the charge level on the 'dummy' row conductors reaches the first level.

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Somerville, NJ, United States of America

Joel Roy Oberman