International Business Machines Corporation

Agere Systems Inc.

Joel Roger Davidson

Alexander Erik Mericas

Mauricio Calle

James Thomas Kirk

Judith E K Laurens

Kevin Franklin Reick

Michael Stephen Floyd

Hehching Harry Li

Betty Ann McDaniel

Michael W Hathaway

Judith K Laurens

Gregg Alan Bouchard

Paul Joseph Jordan

Praveen S Reddy

Sanjay Raghunath Deshpande

Manuel Joseph Alvarez, Ii

Nandor G Thoma

Peter Dau Geiger

John Edward Derrick

Lawrence Joseph Powell, Jr

Humberto Felipe Casal

Joel M Tendler

Christopher Brian Walton

Franklin Mark Liu

Trong Duc Nguyen

Campbell H Snyder

Hung Oui Le

Yuan C Lo

Maurice A Uebelhor

A packet processing system comprises first processing circuitry for performing a first function, and first memory circuitry coupled to the first processing circuitry for storing received packets, wherein at least a portion of the packets stored by the first memory circuitry are usable by the first processing circuitry in accordance with the first function. The packet processing system further comprises at least second processing circuitry for performing a second function, and at least second memory circuitry coupled to the second processing circuitry for storing at least a portion of the same packets stored in the first memory circuitry, wherein at least a portion of the packets stored in the second memory circuitry are usable by the second processing circuitry in accordance with the second function. In an illustrative embodiment, the first processing circuitry and the second processing circuitry operate in a packet switching device such as a router. In such case, the first processing circuitry and the second processing circuitry operate between a packet network interface and a switch fabric of the packet switching device.

Methods and apparatus for using multiple reassembly memories for performing multiple functions

A network processor or other type of processor includes a packet analyzer and first memory circuitry operatively coupled to the packet analyzer. The packet analyzer is operative to at least partially analyze one or more packets received by the processor in order to determine for a given one of the packets a portion of the packet to be stored in the first memory circuitry. The portion of the given packet when stored in the first memory circuitry is thereby made accessible for subsequent processing within the processor, without requiring access to second memory circuitry associated with the processor and configured to store substantially the entire given packet. The packet analyzer may be configured to utilize a value stored in a register of the processor to determine the portion of the given packet to be stored in the first memory circuitry. The register may be one of a number of registers which implement a look-up table accessible to the packet analyzer. The look-up table includes multiple entries, each having packet categorizing information, such as port number or packet flow identifier, and an associated number of blocks of the packet to be stored in the first memory circuitry. The value stored in a given one of the registers may be dynamically updatable under control of a host device operatively coupled to the processor.

Processor with reduced memory requirements for high-speed routing and switching of packets

A network processor or other type of processor includes in an illustrative embodiment a first pass classifier coupled to first memory circuitry in the form of a relatively small internal memory, and a second pass classifier coupled to second memory circuitry in the form of a larger internal buffer memory. The first memory circuitry is configurable to store at least a portion of a given packet to be processed by the first pass classifier. The second memory circuitry is configurable to store a different and preferably smaller portion of the given packet to permit processing thereof by the second pass classifier. The portion of the given packet storable in the second memory circuitry is a portion of the given packet determined by a first pass classification, performed by the first pass classifier, to be required for a second pass classification, performed by the second pass classifier. Advantageously, the invention reduces the size of the packet portion required to be stored in the second memory circuitry, thereby reducing the required memory of the processor. The processor may be configured as a network processor integrated circuit to provide an interface between a network from which the packet is received and a switch fabric in a router or switch.

Method and apparatus for classification of packet data prior to storage in processor buffer memory

A network processor or other type of processor includes first classification circuitry, scheduling circuitry and second classification circuitry. The first classification circuitry is configured to determine for a given packet received by the processor whether the packet has one or more errors. The scheduling circuitry in an illustrative embodiment receives an indication of the error determination made by the first classification circuitry, and based on the indication controls the dropping of the given packet from the processor memories if the packet has one or more errors, e.g., via a flush transmit command. The second classification circuitry, which may be implemented as a single classification engine or a set of such engines, may be configured to perform at least one classification operation for the given packet, e.g., if the packet is supplied thereto by the scheduling circuitry.

Processor with packet data flushing feature

A method and apparatus for reassembling data blocks back into their constituent data packets in a network processor. Each data block associated with a packet is assigned a unique queue identifier for use in assembling all blocks from the same packet. The packet is also assigned a packet identifier, a start of packet identifier and an end of packet identifier for use by downstream network processors to process the packet. The blocks are assembled according to the assigned queue identifier until the last block of a packet is received, at which time the packet reassembly is complete.

Method and apparatus for reassembly of data blocks within a network processor

A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. The node controller receives commands from a master device, communicates with a master device as another master device or as a slave device, and queues commands received from a master device. Due to pin limitations that may be caused by large buses, e.g. buses that support a high number of data pins, the node controller may be implemented such that the functionality for its address paths and data paths are implemented in physically separate components, chips, or circuitry, such as a node data controller or a node address controller. In this case, commands may be sent from the node address controller to the node data controller to control the flow of data through a node.

Method and system for controlling data transfers with physical separation of data functionality from address and control functionality in a distributed multi-bus multiprocessor system

A microprocessor including a performance monitor unit is disclosed. The performance monitor unit includes a set of performance monitor counters and a corresponding set of control circuits and programmable control registers. The performance monitor unit receives a first set of event signals from functional units of the processor. Each of the first set of events is routed directly from the appropriate functional unit to the performance monitor unit. The performance monitor unit further receives at least a second set of event signals. In one embodiment, the second set of event signals is received via a performance monitor bus of the processor. The performance monitor bus is typically a shared bus that may receive signals from any of the functional units of the processor. The functional units may include multiplexing circuitry that determines which of the functional units has mastership of the shared bus. Whereas the performance monitor unit is typically capable of monitoring the direct event signals in any of its counters, the indirect event signals may be selectively routed to the counters. The shared bus may be divided into sub-groups or byte lanes where the byte lanes are selectively routed to the set of performance monitor counters. The state of a control register may determine the event that is monitored in the corresponding counter. In one embodiment, the control register provides a set of signals that are connected to the select inputs of one or more multiplexers. The multiplexers receive multiple events signals and, based on the state of their select signals, route one of the received event signals to the corresponding performance monitor counter. Specified states of the select signals may result in the disabling of the corresponding counter or enabling the counter to count system clock cycles rather than any performance event.

Hierarchical selection of direct and indirect counting events in a performance monitor unit

A multi-stage byte lane selectable bus. In a preferred embodiment, the bus in performance monitor mode includes a plurality of byte lanes and a selection mechanism. The selection mechanism acquires, from a plurality of signals, a subset of those signals, which are desired to be monitored, and places this subset of signals on the byte lanes that are input to the PMU. The number of the plurality of signals that potentially may be monitored is greater than the number of byte lanes and is also greater than the number of PMU counters.

Method and apparatus for a byte lane selectable performance monitor bus

A method and apparatus for selecting an instruction to be monitored within a pipelined processor in a data processing system is presented. A plurality of instructions are fetched, and the plurality of instructions are matched against at least one match condition to generate instructions that are eligible for sampling. The match conditions may include matching the opcode of an instruction, the pre-decode bits of an instruction, a type of instruction, or other conditions. The matched instructions may be marked using a match bit that accompanies the instruction through the selection process. The instructions eligible for sampling are then sampled to generate a sampled instruction. A sampled instruction may be marked with a sample bit that accompanies the instruction through the instruction execution process in order to monitor the sampled instruction while it is executing within the pipelined processor.

Method and apparatus for instruction sampling for performance monitoring and debug

A method and system for detecting flushed instructions without a flush indicator is provided. In order to monitor the flushing of an instruction in an instruction pipeline of a processor, an instruction is selected as a sampled instruction and the progress of the sampled instruction through the instruction pipeline is monitored. Upon selection of an instruction as a sampled instruction, a countdown value is initialized to a value equal to the maximum number of instructions within the instruction pipeline, and as instructions complete, the countdown value is decremented. If progress of the sampled instruction is detected as the instruction moves through the instruction pipeline, the countdown value is reinitialized. If the countdown value reaches zero, then a flush of the sampled instruction from the instruction pipeline is presumed, and an indication that the sampled instruction has been flushed is generated. In response to the indication that the sampled instruction has been flushed, a subsequent instruction may be selected as a subsequently sampled instruction.

Method and system for detecting a flush of an instruction without a flush indicator

A method and apparatus for selecting an instruction to be monitored within a pipelined processor is presented. One or more pairs of match values stored in control registers are allocated for use in instruction sampling or instruction matching. These pairs, referred to as V and V are used together to filter instructions for sampling or for instruction matching. During the fetch or decode stage, the instruction word is compared bit by bit to the V and V pair(s). For each bit in the instruction word, the corresponding bit in V and V are used to determine if a match exists. If every bit position in the instruction word results in a match, the instruction is eligible for sampling. If any bit position does not match, the instruction is not eligible. In response to a determination that the instruction is eligible for sampling, the execution of the instruction may be monitored.

Method and apparatus for identifying instructions for performance monitoring in a microprocessor

A method and apparatus for monitoring an internal queue within a processor, such as an instruction completion table or instruction re-order buffer, is presented. The performance monitoring unit of the processor contains multiple counters, and each counter counts occurrences of specified events. An internal queue of the processor may be specified to be monitored. A count of event signals indicating a successful allocation request for an entry in the internal queue is divided by a count of event signals indicating a passage of units of time to obtain the average rate for allocation requests for queue entries in the specified internal queue. A count of event signals indicating an occupation of a specific entry in the internal queue during a unit of time is divided by a count of event signals indicating an allocation of a specific entry in the internal queue to obtain the average time spent in the internal queue. An average number of entries in the internal queue is computed as a product of the average rate for allocation requests for queue entries and the average time spent in the internal queue. An event signal that indicates failure of an allocation request for an entry in the internal queue may be monitored.

Method and apparatus for monitoring the performance of internal queues in a microprocessor

A method and system for monitoring the performance of a instruction pipeline is provided. The processor may contain a performance monitor for monitoring for the occurrence of an event within a data processing system. An event to be monitored may be specified through software control, and the occurrence of the specified event is monitored during the execution of an instruction in the execution pipeline of the processor. A particular instruction may be specified to execute within a threshold time for each stage of the instruction pipeline. The specified event may be the completion of a single tagged instruction beyond the specified threshold interval for a stage of the instruction pipeline. The performance monitor may contain a number of counters for counting multiple occurrences of specified events during the execution of multiple instructions, in which case the specified events may be the completion of tagged instructions beyond a threshold interval for any stage of the multiple stages of the execution pipeline. As the instruction moves through the processor, the performance monitor collects the events and provides the events for optimization analysis.

Method and system for providing temporal threshold support during performance monitoring of a pipelined processor

A method and system for debugging the execution of an instruction within an instruction pipeline is provided. A processor in a data processing system contains instruction pipeline units. An instruction may be tagged, and in response to an instruction pipeline unit completing its processing of the tagged instruction, a stage completion signal is asserted. An execution monitor external to the pipelined processor monitors the stage completion signals during the execution of the tagged instruction. The execution monitor may be a logic analyzer that displays the stage completion signals in real-time on a display device of the execution monitor. An instruction to be tagged may be selected based upon an instruction selection rule, such as the address of the instruction.

Method and system for tracking the progress of an instruction in an out-of-order processor

A clocking system for complex electronic devices is created in an hierarchial manner whereby the master clock pulse is provided to a plurality of digital pulse aligners which in turn provide phase aligned clock signals at the field replaceable unit level to either a slave clock or a digital phase aligner. The slave clock or the digital phase aligner at the field replaceable unit level in turn provides an aligned clock pulse to a timing node on respective chips. A third level of the hierarchy provides similarly aligned pulses to individual using-circuits on the chips of the system. The digital phase aligner, aligning the output pulse at the timing node of the next level with the reference pulses being provided to the digital phase aligner at each level, insures that the timing pulses arriving at the utilizing circuits are synchronously aligned with clock pulses of the master clock. The system provides dramatic simplification of replacement of either field replaceable units or individual components within field replaceable units. The system is self-phasing and self-correcting to accommodate timing misalignments caused by any variations in the timing delays at all levels, thereby reducing the jitter that must be accommodated.

Growing community of inventors

Austin, TX, United States of America

Joel Roger Davidson