Cadence Design Systems, Inc.

Joel Reuben Phillips

Igor Keller

Vinod Kariat

Saurabh Kumar Tiwary

Kenneth S Kundert

King Ho Tam

Dan Feng

Baolin Yang

Zhenhai Zhu

Luis Guerra E Silva

Luis Miguel Silveira

Mina Adel Aziz Farhan

Louis K Scheffer

Henry C Chang

Ted Vucurevich

Luca Daniel

Jijun Chen

Radu Zlatanovici

Sherry Solden

Ilya Yusim

Anubhav Gupta

Claudio Pinello

Jun Meng

Yunbo Pang

Qunzeng Liu

Yinghong Zhou

Zuochang Ye

Zuo-Chang Ye

Marco Tony Lloyd Kassis

Disclosed are methods, systems, and articles of manufacture for characterizing an electronic design with an MOR-based envelope Fourier technique. Multiple training models may be determined at multiple time points for an electronic circuit by using at least the MOR-based envelope Fourier technique that comprises a harmonic balance technique. A training model of the multiple training models may be reduced into a reduced order training model in a reduced order space at least by applying at least model order reduction of the MOR-based envelope Fourier technique to the training model. A time varying system may be determined for the electronic circuit based by using at least the reduced order training model.

Method, system, and computer program product for characterizing an electronic circuit using model order reduction-based envelope fourier techniques

Various embodiments describe performing a transient simulation of circuits that have mutual inductors. In particular, some embodiments perform a transient simulation on a circuit model by removing and approximating the effects of one or more entries of a matrix in the circuit model, where the matrix relates to inductors or mutual inductors of the circuit. In doing so, such embodiments can render the matrix more sparse than before which, in turn, can reduce the time spent during the transient simulation to solve equations of the circuit model.

Systems and methods for transient simulation of circuits with mutual inductors

A system, method, and computer program product for reduced resource harmonic balance circuit simulations is disclosed, wherein a lattice structure is implemented in place of conventional approaches in order to reduce the amount of data being processed in each iteration of the harmonic balance process. Additionally, sparse frequency cuts, which correspond to the lattice structures, are disclosed. The sparse frequency cuts and the lattice structure may be may be customized, modified, and/or adjusted to match a variety of circuits with non-linear components, such as those found in microwave, RF, and multicarrier (e.g. LTE) implementations.

Reduced resource harmonic balance circuit simulations

The time to test integrated circuits is increasing as a function of the complexity of integrated circuits and processes used to fabricate the integrated circuits. Embodiments of this disclosure include systems and methods for reducing the time to integrated circuits by reducing the number of devices individually modeled. Embodiments can reduce the number of modeled devices by combining two or more devices into a single combined device that models all discrete devices, but in a reduced form.

System and method for efficient device testing and validation of fast transients

In one embodiment of the invention, a multi-CCC current source model is disclosed to perform statistical timing analysis of an integrated circuit design. The multi-CCC current source model includes a voltage waveform transfer function, a voltage dependent current source, and an output capacitor. The voltage waveform transfer function receives an input voltage waveform and transforms it into an intermediate voltage waveform. The voltage dependent current source generates an output current in response to the intermediate voltage waveform. The output capacitor is coupled in parallel to the voltage dependent current source to generate an output voltage waveform for computation of a timing delay.

Static timing analysis methods for integrated circuit designs using a multi-CCC current source model

In one embodiment of the invention, a method for electronic circuit design is disclosed. The method includes analyzing a hierarchy of a netlist of a circuit to determine primary inputs and primary outputs of the circuit at an upper level, and internal vertices of the circuit at lower levels between the primary inputs and the primary outputs; forming a timing graph of the circuit including a plurality of timing delay edges representing timing delay between the primary inputs, the internal vertices and the primary outputs to form a plurality of paths of a path space from the primary inputs to the primary outputs; and in response to the timing delay of the plurality of timing delay edges, dynamically pruning paths of the plurality of paths using branch and bound techniques on bounds of timing delay that are a function of one or more circuit parameters to reduce the path space down to one or more critical timing paths of the circuit with a worse case metric of timing delay between the primary inputs and the primary outputs. Additionally or alternatively, timing in the circuit may be analyzed to determine a bound of timing delay of the circuit for one or more parameter corners in a parameter space and if the bound of timing delay is worse than a threshold time delay then one or more parameter corners may be pruned from the parameter space using branch and bound techniques.

Branch and bound techniques for computation of critical timing conditions

A system and method are disclosed for waveform based variational static timing analysis. A circuit is divided into its linear circuit parts and non-linear circuit parts and modeled together, by a combination of linear modeling techniques, into linear equations that may be represented by matrices. The linear equations in matrix form may be readily solved by a computer such that an input waveform to an input pin of the circuit can be sequentially 'pushed' through the various interconnects and logic networks of the circuit to an output pin. Output voltage waveforms are obtained at each stage of the waveform pushing and may be used to perform static timing analysis.

Waveform based variational static timing analysis

A method is provided for use during static timing analysis of an integrated circuit design to produce an equivalent waveform model, the method comprising: using an analog model of the inner component, to simulate an inner component to produce multiple analog simulation output characterization waveforms as a function of multiple input waveforms used to characterize the design cell; using the analog model of the inner component to simulate the inner component to produce an analog simulation output waveform as a function of the complex waveform; and producing the equivalent waveform model as a function of the multiple analog simulation output characterization waveforms and the analog simulation output waveform.

Generating an equivalent waveform model in static timing analysis

In one embodiment of the invention, a method of statically analyzing an integrated circuit with process and environment variations is provided. The method includes characterizing each circuit cell of a cell library for a sensitivity to process parameter variations within a predetermined range; creating a timing graph corresponding to a netlist representing an integrated circuit design; along nodes of the timing graph, computing delay values including sensitivities to process variations; for each selected output node of the netlist, propagating a full timing value function with the sensitivities to the selected output nodes; and generating a parameterized timing report including the sensitivities to the process variations.

Methods, systems, and apparatus for timing and signal integrity analysis of integrated circuits with semiconductor process variations

In one embodiment, a method of constructing an equivalent waveform model for static timing analysis of integrated circuit designs is disclosed. The method includes fitting time point coefficients (q) and known time delay values from a delay and slew model of a receiving gate from a timing library; determining waveform values (I) for input waveforms from the timing library; determining timing values (d) from a timing table in the timing library in response to the input waveforms of the timing library; and determining coefficients (q) by minimizing a residual of a delay equation.

Equivalent waveform model for static timing analysis of integrated circuit designs

Multi-CCC current source models and static timing analysis methods for integrated circuit designs

Sensitivity and static timing analysis for integrated circuit designs using a multi-CCC current source model

Methods and apparatus for waveform based variational static timing analysis

A method is provided to formally verify a property of a circuit design comprising: receiving a description of at least a portion of the circuit; receiving an indication of search accuracy criteria; receiving a description of a relationship between current and voltage (I-V relationship) for one or more of devices of the circuit; converting each I-V relationship to a conservative approximation of such I-V relationship; assigning voltage labels to one or more terminals of one or more identified devices that indicate voltage relationships among the one or more terminals consistent with KVL; defining a respective current relationship among one or more respective sets of currents of the one or more of the identified devices that is consistent with KCL; searching for one or more combinations of current and voltage values that are within at least one region of each conservative approximation and that are consistent with the voltage labels and that are consistent with each respective defined current relationship; converting each region determined to have a searched for combination of current and voltage values to multiple respective smaller regions; and repeating the acts of searching and converting until regions are obtained that meet the received search accuracy criteria.

Boolean satisfiability based verification of analog circuits

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Oakland, CA, United States of America

Joel Reuben Phillips