Nxp Usa, Inc.

Joel Ray Knight

Stefano Pietri

James B Eifert

Thomas Henry Luedeke

Anurag Jindal

Stefan Doll

Nikila Krishnamoorthy

Steven K Watkins

Hubert Glenn Carson, Jr

Hilario Manuel Garza

Kamel Musa Khalaf

Adrian Lee Carleton

A fully digital integrated circuit apparatus () and method () are provided for generating a test mode enable signal with a digital non-resettable state retention storage circuit () connected to store an authentication control pattern for authorizing test mode access to a secure circuit, a digital safety interlock gate circuit () connected to store a safety interlock gate setting that may be accessed independently from a test mode enable signal, and combinatorial logic circuitry () for generating the test mode enable signal only when the interlock safety gate setting is set to a first value and the digital non-resettable state retention storage circuit stores the authentication control code.

Method and apparatus for digital only secure test mode entry

An integrated circuit includes a normal voltage detector configured to detect a normal voltage at which the integrated circuit being fully functional. A first voltage detector detects a first voltage that is less than the normal voltage. A second voltage detector detects a second voltage that is less than the first voltage. A reset module is coupled to a supply voltage, the normal voltage detector, the first voltage detector, and the second voltage detector. The reset module includes test logic to, when the supply voltage rises to the first voltage from the second voltage, perform a pass/fail test when the integrated circuit is in a pass/fail test mode, and perform a power up reset when the integrated circuit in not in the pass/fail test mode.

Secure low voltage testing

Growing community of inventors

Austin, TX, United States of America

Joel Ray Knight