International Business Machines Corporation

Globalfoundries Inc.

Toshiba America Electronic Components, Inc.

Joel Pereira De Souza

Devendra K Sadana

Yun Seog Lee

Stephen W Bedell

Keith E Fogel

Jeehwan Kim

Ning Li

Alexander Reznicek

John C Collins

Ali Afzali-Ardakani

Bahman Hekmatshoartabari

Brent A Wacaser

Ghavam G Shahidi

Katherine Lynn Saenger

Dominic Joseph Schepis

Thomas N Adam

John Albrecht Ott

Daniel Michael Kuchta

Teodor Krassimirov Todorov

Babar Ali Khan

Siegfried Lutz Maurer

Marinus Hopstaken

Kunal Mukherjee

Kangguo Cheng

Ali Khakifirooz

Arvind Kumar

Seyoung Kim

Talia S Gershon

Steven John Koester

Edward William Kiewra

Shahab Siddiqui

Christopher Carr Parks

Daniel Aneurin Inns

Takashi Ando

Shogo Mochizuki

Haining S Yang

Dechao Guo

Hemanth Jagannathan

Ruqiang Bao

Soon-Cheon Seo

Eduard Albert Cartier

Brian Joseph Greene

Hiroyuki Miyazoe

Kevin W Brew

Harold John Hovel

Dexin Kong

Karen A Nummy

Gen Tsutsui

Stephan Alan Cohen

Youngseok Kim

Thomas A Wallner

Yao Yao

Daniel J Poindexter

Kevin K Chan

Davood Shahrjerdi

Christian Lavoie

Zhen Zhang

Robert David Allen

Tze-Chiang Chen

Ahmet Serkan Ozcan

Kathryn Turner Schonenberg

Young-Hye Na

Donald Rene Wall

Jangwoo Kim

Marinus J P Hopstaken

Masafumi Hamaguchi

Whitney T Byron

Embodiments of the invention provide a resistive switching device that includes a metal interconnect electrode and a charge-particle-treated memory stack over the metal interconnect electrode. The charge-particle-treated memory stack includes a plurality of layers that includes a top electrode, a bottom electrode, and a dielectric layer between the top electrode and the bottom electrode. The dielectric layer includes a portion of a blanket dielectric layer. The bottom electrode includes a portion of a blanket bottom electrode layer. The charge-particle-treated memory stack further includes a current-conducting filament characteristic that results from charge particle treatments applied while a top surface of the blanket dielectric layer is exposed and a top surface of the blanket bottom electrode is exposed.

Oxide-based resistive memory having a plasma-exposed bottom electrode

A method of forming a solid-state lithium ion rechargeable battery may include depositing a metal layer onto a top surface of a substrate, depositing a handle layer onto a top surface of the metal layer, wherein a portion of the handle layer overlaps the metal layer and the substrate, spalling a portion of the substrate thereby forming a spalled substrate layer, porosifying the spalled substrate layer thereby forming a porous substrate layer, depositing an electrolyte layer onto a top surface of the porous substrate layer, wherein the electrolyte layer is in direct contact with the porous substrate layer, and depositing a cathode onto a top surface of the electrolyte layer. The method may include depositing a cathode contact layer onto a top surface of the cathode, wherein the cathode contact layer is in direct contact with the cathode. The porous substrate layer may be made of silicon.

Solid state lithium ion rechargeable battery

A Phase-Change Memory (PCM) device includes a dielectric layer, a bottom electrode disposed in the dielectric layer, a liner material disposed on the bottom electrode, a phase-change material disposed on the liner material, and a top electrode disposed on the phase-change material and in the dielectric layer.

Phase-change memory (PCM) including liner reducing resistance drift

A silicon-based electrode forms an interface with a layer pair being: 1. a thin, semi-dielectric layer made of a lithium (Li) compound, e.g. lithium fluoride, LiF, disposed on and adheres to the electrode surface of the silicon-based electrode and 2. an molten-ion conductive layer of a lithium containing salt (lithium salt layer) disposed on the semi-dielectric layer. One or more device layers can be disposed on the layer pair to make devices such as energy storage devices, like batteries. The interface has a low resistivity that reduces the energy losses and generated heat of the devices.

Low resistance composite silicon-based electrode

Provided are embodiments for a semiconductor device. The semiconductor device includes a bottom electrode, wherein the bottom electrode is formed on a metal interconnect electrode, and a dielectric layer on a surface of the bottom electrode. The semiconductor device also includes a top electrode formed on a surface of the dielectric layer, wherein at least one of the top electrode or the bottom electrode is a plasma treated top electrode or plasma treated bottom electrode. Also provided are embodiments for a method of fabricating a resistive switching device where at least one of the plurality of layers of the memory stack is processed with a charge particle treatment.

Methods of forming a controllable resistive element include forming source and drain regions in a substrate. A battery stack is formed on a substrate between the source and drain regions. Respective anode and cathode electrical connections are formed to the battery stack. Respective source and drain electrical connections are formed.

Battery-based neural network weights

A semiconductor device includes an extremely thin semiconductor-on-insulator substrate (ETSOI) having a base substrate, a thin semiconductor layer and a buried dielectric therebetween. A device channel is formed in the thin semiconductor layer. Source and drain regions are formed at opposing positions relative to the device channel. The source and drain regions include an n-type material deposited on the buried dielectric within a thickness of the thin semiconductor layer. A gate structure is formed over the device channel.

Leakage-free implantation-free ETSOI transistors

A semiconductor device includes a field-effect transistor, a first back-end-of-line (BEOL) metallization level and a second BEOL metallization level disposed above the first BEOL metallization level. A portion of the field-effect transistor includes lithium therein, and the field-effect transistor is integrated between the first and second BEOL metallization levels. The portion of the field-effect transistor including the lithium therein can be a channel layer, or a source and/or drain region.

Lithium drifted thin film transistors for neuromorphic computing

An energy storage device is provided that includes a pre-lithiated silicon based anode and a carbon nanotube based cathode. The pre-lithiated silicon anode has a porous region and a non-porous region. The full cell energy storage device has high electrochemical performance which exhibits greater 200 rechargeable cycles with less than 25% after 10 charge discharge cycles relative to the first discharge cycle, a maximum specific discharge capacity greater than 300 mAh/g and a specific capacity of greater than 100 mAh/g for over 130 cycles. Such an energy storage device is scalable for a wide array of applications due to its wafer level processing and silicon-based substrate integrability.

Energy storage device containing a pre-lithiated silicon based anode and a carbon nanotube based cathode

A battery includes a cathode with a metal halide and an electrically conductive material, wherein the metal halide acts as an active cathode material; a porous silicon anode with a surface having pores with a depth of about 0.5 microns to about 500 microns, and a metal on the surface and in at least some of the pores thereof; and an electrolyte contacting the anode and the cathode, wherein the electrolyte includes a nitrile moiety.

Porous silicon anode for rechargeable metal halide battery

A catholyte-like material including a cathode material and an interfacial additive layer for providing a lithium ion energy storage device having low impedance is disclosed. The interfacial additive layer, which is composed of vapor deposited iodine, is present between the cathode material and an electrolyte layer of the device. The presence of such an interfacial additive layer increases the ion and electron mobile dependent performances at the cathode material interface due to significant decrease in the resistance/impedance that is observed at the respective interface as well as the impedance observed in the bulk of the device. The catholyte-like material of the present application can be used to provide a lithium ion energy storage device having high charge/discharge rates and/or high capacity.

Lithium ion energy storage device containing a vapor deposited iodine interfacial layer

An interfacial additive layer for decreasing the interfacial resistance/impedance of a silicon based electrode-containing device such as, for example, an energy storage device or a micro-resistor, is disclosed. The interfacial additive layer, which is composed of a molten lithium containing salt, is formed between a silicon based electrode and a solid polymer electrolyte layer of the device. The presence of such an interfacial additive layer increases the ion and electron mobile dependent performances at the silicon based electrode interface due to significant decrease in the resistance/impedance that is observed at the respective interface as well as the impedance observed in the bulk of the device.

Molten ion conductive salt/silicon interface for decreased interfacial resistance

A method of forming a semiconductor structure includes forming at least one trench in a non-porous silicon substrate, the at least one trench providing an energy storage device containment feature. The method also includes forming an electrical and ionic insulating layer disposed over a top surface of the non-porous silicon substrate. The method further includes forming, in at least a base of the at least one trench, a porous silicon layer of unitary construction with the non-porous silicon substrate. The porous silicon layer provides at least a portion of a first active electrode for an energy storage device disposed in the energy storage device containment feature.

Silicon substrate containing integrated porous silicon electrodes for energy storage devices

A device such as, for example, an energy storage device or a micro-resistor, is disclosed which includes a silicon based electrode in which decreased interfacial resistance/impedance throughout the charge-mobile region of the device is provided. The decreased interfacial resistance/impedance is provided by forming an interfacial additive composite layer composed of a molten lithium containing salt layer and a layer of a Li-salt containing conductive polymeric adhesive material between the silicon based electrode and a solid polymer electrolyte layer. The presence of such an interfacial additive composite layer increases the ion and electron mobile dependent performances at the silicon based electrode interface due to significant decrease in the resistance/impedance that is observed at the respective interface as well as the impedance observed in the bulk of the device.

Polymer and molten ion conductive salt and silicon interface for decreased interfacial resistance

Embodiments of the invention are directed to a resistive switching device (RSD). A non-limiting example of the RSD includes a fin-shaped element formed on a substrate, wherein the fin-shaped element includes a source region, a central channel region, and a drain region. A gate is formed over a top surface and sidewalls of the central channel region. The fin-shaped element is doped with impurities that generate interstitial charged particles configured to move interstitially through a lattice structure of the fin-shaped element under the influence of an electric field applied to the RSD.

FinFET resistive switching device having interstitial charged particles for memory and computational applications

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Putnam Valley, NY, United States of America

Joel Pereira De Souza