Lam Research Corporation

Applied Materials, Inc.

Joel M Cook

Fred Conrad Redeker

John Boyd

Yezdi N Dordi

William Thie

Thomas E Wicker

Janet M Flanner

Linda N Marquez

Bob Maraschin

Andrew D Bailey, Iii

David J Hemker

William S Kennedy

Robert A Maraschin

Shrikant Lohokare

Ian J Morey

Eric A Hudson

Neil M Benjamin

Jian J Chen

Alan M Schoepp

John R Trow

Jaroslaw Walery Winniczek

Helen Louise Maynard

Adrian Doe

Prashant Gadgil

Broadly speaking, a method and an apparatus are provided for depositing a material on a semiconductor wafer ('wafer'). More specifically, the method and apparatus provide for selective heating of a surface of the wafer exposed to an electroless plating solution. The selective heating is provided by applying radiant energy to the wafer surface. The selective heating of the wafer surface causes a temperature increase at an interface between the wafer surface and the electroless plating solution. The temperature increase at the interface in turn causes a plating reaction to occur at the wafer surface. Thus, material is deposited on the wafer surface through an electroless plating reaction that is initiated and controlled by varying the temperature of the wafer surface using an appropriately defined radiant energy source.

Method and apparatus for material deposition

Method for electroless depositing a material on a surface of a wafer

Method and apparatus for material deposition in semiconductor fabrication

Processes for treating a morphologically-modified surface of a silicon upper electrode of a plasma processing chamber include exposing the surface to a gas composition containing at least one gas-phase halogen fluoride. The gas composition is effective to remove silicon from the morphologically-modified surface and restore the surface state.

Processes for treating morphologically-modified silicon electrode surfaces using gas-phase interhalogens

A system and method for planarizing a patterned semiconductor substrate includes receiving a patterned semiconductor substrate. The patterned semiconductor substrate having a conductive interconnect material filling multiple of features in the pattern. The conductive interconnect material having an overburden portion. The overburden portion having a localized non-uniformity. A bulk portion of the overburden portion is removed to planarize the overburden portion. The substantially locally planarized overburden portion is mapped to determine a global non-uniformity. The substantially locally planarized overburden portion is etched to substantially remove the global non-uniformity.

System, method and apparatus for improved global dual-damascene planarization

A system and method for planarizing a patterned semiconductor substrate includes receiving a patterned semiconductor substrate. The patterned semiconductor substrate having a conductive interconnect material filling multiple of features in the pattern. The conductive interconnect material having an overburden portion. The overburden portion includes a localized non-uniformity. An additional layer is formed on the overburden portion. The additional layer and the overburden portion are planarized. The planarizing process substantially entirely removes the additional layer.

System, method and apparatus for improved local dual-damascene planarization

In a plasma processing system for processing substrates such as semiconductor wafers, deposition of polymer in an area between a focus ring and an electrostatic chuck in a plasma processing chamber is achieved by providing a clearance gas in a gap between the chuck and the focus ring. A series of channels delivers the clearance gas to the annular gap between the outer surface of the substrate support and the inner surface of the focus ring surrounding the substrate support. The clearance gas supplied to the annular gap is preferably a gas such as helium which will not affect the wafer processing operation. In the case of plasma etching, the clearance gas is supplied at a flow rate which is sufficient to block the migration of process gas and volative byproducts thereof into the annular gap without adversely affecting edge etch performance.

Apparatus for reducing polymer deposition on substrate support

Disclosed are methods and systems for etching dielectric layers in a high density plasma etcher. A method includes providing a wafer having a photoresist mask over a dielectric layer in order to define at least one contact via hole or open area that is electrically interconnected down to the silicon substrate of the wafer. The method then proceeds to inserting the wafer into the high density plasma etcher and pulsed application a TCP power source of the high density plasma etcher. The pulsed application includes ascertaining a desired etch performance characteristic, which includes photoresist selectivity and etch rate which is associated with a continuous wave application of the TCP source. Then, selecting a duty cycle of the pulsed application of the TCP source and scaling a peak power of the pulsed application of the TCP source in order to match a cycle-averaged power that would be delivered by the continuous wave application of the TCP source. The pulsed application of the TCP power source is configured to etch through the dielectric layer to at least one contact via hole or open area while substantially reducing damage to the transistor gate oxides of the transistor devices.

Methods for running a high density plasma etcher to achieve reduced transistor device damage

In a plasma processing chamber, a method for etching through a selected portion of an oxide layer of a wafer's layer stack to create a self-aligned contact opening is described. The wafer stack includes a substrate, a polysilicon layer disposed above the substrate, a nitride layer disposed above said polysilicon layer and the oxide layer disposed above the nitride layer. The method for etching includes etching through the oxide layer of the layer stack with a chemistry and a set of process parameters. The chemistry essentially includes C.sub.2 HF.sub.5 and CH.sub.2 F.sub.2 and the set of process parameters facilitate etching through the oxide layer without creating a spiked etch and etching the oxide layer through to the substrate without substantially damaging the nitride layer.

Self-aligned contacts for semiconductor device

The invention relates to a plasma processing reactor for processing a substrate. The plasma processing reactor includes a process chamber. The plasma processing reactor further includes an inductive coil configured to be coupled to a RF power source having a RF frequency wherein the inductive coil generates an electric field inside of the process chamber. The plasma processing reactor additionally includes a magnetic field producing device configured to produce a magnetic field inside the process chamber in proximity of the electric field.

Method for igniting a plasma inside a plasma processing reactor

A plasma processing chamber includes a substrate holder and a dielectric member such as a dielectric window or gas distribution plate having an interior surface facing the substrate holder, the interior surface being maintained below a threshold temperature to minimize process drift during processing of substrates. The chamber can include an antenna which inductively couples RF energy through the dielectric member to energize process gas into a plasma state. The antenna can include a channel through which a temperature controlling fluid, which has been cooled by a closed circuit temperature controller, is passed. The control of the temperature of the interior surface minimizes process drift and degradation of the quality of the processed substrates during sequential batch processing of substrates such as during oxide etching of semiconductor wafers.

Temperature controlling method and apparatus for a plasma processing

A method in a plasma processing chamber for fabricating a semiconductor device having a self-aligned contact. The method includes the step of providing a wafer having a substrate, a polysilicon layer disposed above the substrate, a nitride layer disposed above a polysilicon layer, and an oxide layer disposed above the nitride layer. The method further includes the step of etching in a first etching step partially through the oxide layer of the layer stack with a first chemistry and a first set of process parameters. In this first etching step, the first chemistry comprises essentially of CHF.sub.3 and C.sub.2 HF.sub.5. The method also includes the step of etching the oxide layer in a second etching step through to the substrate with a second chemistry comprising CHF.sub.3 and C.sub.2 HF.sub.5 and a second set of process parameters. The second set of process parameters is different from the first set of process parameters and represents a set of parameters for etching the oxide layer with a higher oxide-to-nitride selectivity than the oxide-to-nitride selectivity achieved in the first etching step.

Methods and apparatus for etching self-aligned contacts

A plasma etch reactor comprising a remote source of plasma mounted on a vacuum processing chamber has a large permanent magnet ring around the area of the chamber where the plasma enters, magnetically oriented so that magnetic field lines are removed from said plasma in the processing chamber, and two or more pairs of magnet rings mounted around said chamber to form a series of magnetic cusps about the wall of said chamber, to thereby inhibit plasma electrons from striking the wall of said chamber. A substrate entry port can be fitted between the magnet rings, allowing automatic ingress and egress of said substrates with maximum efficiency.

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Warrenton, VA, United States of America

Joel M Cook