M/a -com, Inc.

The Whitaker Corporation

Tyco Electronics Corporation

Macom Technology Solutions Holdings, Inc.

Mia-com, Inc.

Teraburst Networks, Inc.

Joel Lee Goodrich

Timothy Edward Boles

Christopher C Souchuns

Bruce A Reardon

James Joseph Brogle

Noyan Kinayman

David Hoag

Jules D Levine

Albert L Armstrong, Jr

Nitin Jain

Matthew F O'Keefe

Percy Bomi Chinoy

Paulette Rita Noonan

Daniel G Curcio

Iqbal K Bansal

James Garfield Loring, Jr

Thomas Robert Lally

Donald Cordeiro

Ross A La Rue

Brian Rizzi

A PIN diode comprising an N-type substrate comprising a cathode of the PIN diode and having an intrinsic layer disposed upon the N-type substrate and having a top surface a P-type material disposed upon the top surface of the intrinsic layer comprising an anode of the PIN diode and a N-type material disposed over the sidewall of the cathode and over the sidewall and a portion of the top surface of the intrinsic material that is not occupied by the anode, wherein a horizontal gap is defined between the anode and the cathode through the intrinsic material, the gap being variable in width and/or the horizontal gap is less than the thickness of the intrinsic layer.

PIN diode with improved power limiting

A light emitting diode package and method of manufacturing the light emitting diode package are provided. The light emitting diode package includes a sub-mount portion and a frame portion extending from the sub-mount portion. The frame portion has angled walls and is configured to receive a light emitting diode therein.

Light emitting diode package

An electric component package having a base and a lid, the base and lid defining a hermetically sealed cavity therebetween for accommodating an electric component. The base includes at least one conductive via extending therethrough, allowing control and/or input/output (I/O) ports associated with the electric component to be coupled to the conducive vias to pass signals between the sealed cavity and the exterior of the package without passing through the junction between the base and lid. The electric component package can be produced at the wafer level using conventional silicon wafer integrated circuit manufacturing machinery prior to separating the wafer into a plurality of devices.

Hermetic electric component package

A method and apparatus are disclosed for reducing crosstalk and dispersion in a crosspoint monolithic microwave integrated circuit (MMIC) switch array operating in a range between DC and microwave frequencies. In accordance with an exemplary embodiment, the crosspoint MMIC switch array includes a dielectric stack, a substrate, a first ground plane, a plurality of thyristor switches, a plurality of signal transmission lines arranged in rows; and a plurality of signal transmission lines arranged in columns. The plurality of signal transmission lines arranged in columns intersect the plurality of signal transmission lines arranged in rows at a plurality of intersection points. Each of the plurality of thyristor switches is associated with one of the plurality of intersection points. Each of the plurality of thyristor switches is in electrical contact with the signal transmission lines that intersect at the associated intersection point.

Crosstalk reduction in a crosspoint thyristor switching array using a shielded dielectric stack

At least one silicon wafer is loaded into a closed vessel that contains a first solution that includes ammonium hydroxide, hydrogen peroxide and DI water. This acidic solution is removed from the vessel and DI water is introduced into the vessel until wafers are completely immersed. The DI water is then removed from the vessel and a second solution that includes hydrofluoric acid, hydrochloric acid solution and DI water is added to the vessel to fully immerse the wafer. The second solution is then removed from the vessel, and as the second solution is being drained from the vessel, an alcohol solution in a hot and low-pressure nitrogen carrier gas is introduced to the vessel, such that as the level of the liquid within the vessel falls below the height of the wafer within the vessel, the surface of the wafer is dried due to surface tension. The thin coating of alcohol solvent on the wafer ensures that the surface of the wafer is hydrogen terminated, thus hydrophobic. The technique of the present invention occurs in a single vessel.

In-situ method for producing a hydrogen terminated hydrophobic surface on a silicon wafer

A method of fabricating a hyperabrupt junction varactor diode structure comprises the steps of forming a non-uniformly doped n-type, hyperabrupt cathode region in a layer of semiconductor material and depositing, by ultra high vacuum chemical vapor deposition (UHVCVD), a p-type anode region onto a surface of the hyperabrupt cathode region. The deposition process is performed at relatively low temperature (i.e., below 600&deg; C.). The anode region and the hyperabrupt cathode are joined at a junction between them such that an impurity concentration level of the hyperabrupt region increases in a direction toward the junction. During the forming step, n-type impurity ions are implanted at an implantation energy level substantially less than 300 keV, preferably between from about 10 to about 70 keV, with the implanted ions being thermally activated at a relatively low temperature (between from about 700 to about 800&deg; C.).

Method of fabricating a variable capacity diode having a hyperabrupt junction profile

A process for fabricating heterolithic microwave integrated circuits. According to one exemplary embodiment, a glass substrate is fused to a silicon wafer, and the silicon wafer is etched to effect silicon pedestals. A glass layer is fused onto and about the silicon mesas and effectively polished to expose the tops of the silicon mesas. The backside glass layer is then polished to render a final thickness of the dielectric layer between the top surface and ground plane. In another exemplary embodiment, a layer of silicon may be selectively etched to form mesas that function as either pedestals or vias. A layer of glass may be fused to the silicon prior to etching. A layer of glass is fused to the silicon substrate and pedestals and planarized through standard polishing techniques. The wafer may be 'flipped over' and polished in order to remove a substantial portion of the silicon or glass, depending on which is used. Thereafter, the integrated circuit is fabricated through standard techniques.

Method of fabricating heterolithic microwave integrated circuits

Silicon conductive vias and pedestals are disclosed for use in microwave integrated circuits. The pedestals are isolated from a ground plane on the bottom surface by glass, while the vias are used to make electrical contact to ground. Electrical circuit elements in the top surface of the integrated circuit are selectively grounded or isolated by the choice of connection to a via or pedestal, respectively.

Heterolithic microwave integrated circuits

A voltage controlled oscillator includes a varactor (201) and a transistor (202) and a ground via (203), of epitaxially grown silicon that is etched to provide respective pedestals embodying the varactor (201) and the transistor (202) and the ground via (203), an L-C resonator circuit, the varactor (201) and an inductor providing a tank circuit that changes the frequency of the L-C resonator circuit, and that shifts the average frequency of the oscillator to that of an input voltage to the collector of the transistor (202).

Heterolithic voltage controlled oscillator

It has been identified that a known loss mechanism in the access path to a mesa type device is more significant than previously believed. The source of the loss is due to the electromagnetic interaction of the wire bond and the device side wall which induces an image current at the side wall along the path of the wire bond. According to the teachings of the present invention, a process for forming a conductive coating on a semiconductor device is disclosed. The coating reduces high frequency losses associated with the device. The processes disclosed are compatible with existing semiconductor fabrication devices and advantageously provide improved uniformity and repeatability.

Process for reducing bond resistance in semiconductor devices and

A process to form integrated circuits comprising silver metal circuits. Deposition techniques such as sputtering, not plating, upon substrates to form such silver metal circuits are common. However in the conventional processes to remove the resist and the metal overlaying the resist, these conventional processes are deleterious to the silver metal. Thereby a new process is provided. This new process entails the metal overlaying the resist of the wafer is initially removed by a high pressure force. The resist, in this new process, is then removed by a benign stripper solution having the temperature of the solution raised to the highest temperature without degrading the stripper solution and said circuit is exposed to said stripper solution for one to five minutes.

Process to preserve silver metal while forming integrated circuits

A mesa-type PIN diode and method for making same are disclosed. A diode made according to the present invention includes a junction formed in the top surface of the mesa-shaped structure, having an area that is less than (and preferrably, approximately half) the area of the top surface. A highly-doped, N-type conducting layer is formed in the side-walls of the mesa-shaped structure. The resulting diode is subject to greatly reduced charge carrier recombination effects and suffers from much less carrier-to-carrier scattering than conventional diodes. Thus, a diode made according to the present invention is capable of achieving much higher stored charge, lower resistance, lower capacitance, better switching characteristics, and lower power consumption than one made according to the prior art. Particular utility is found, inter alia, in the areas of high-frequency microwave and monolithic circuits.

Mesa type PIN diode

Method for making a mesa type PIN diode

A semiconductor device and associated method of fabrication in which the device includes a semiconductor substrate having a cavity therein extending in a frame pattern. An insulating layer such as one of silicon nitride is deposited in the cavity followed by the deposition of polysilicon to substantially fill the cavity and provide structural support. An epitaxy layer is formed over the surface of the substrate along with a second insulating layer having windows defined therein for enabling ohmic contact with the epitaxy layer and substrate, resectively. Metallization is deposited to form separate beam leads to provide ohmic contact at the epitaxy layer and substrate.

Method of fabricating a semiconductor beam lead device

A semiconductor device and associated method of fabrication in which the device includes a semiconductor substrate having a cavity therein extending in a frame pattern. An insulating layer such as one of silicon nitride is deposited in the cavity followed by the deposition of polysilicon to substantially fill the cavity and provide structural support. An epitaxy layer is formed over the surface of the substrate along with a second insulating layer having windows defined therein for enabling ohmic contact with the epitaxy layer and substrate, respectively. Metallization is deposited to form separate beam leads to provide ohmic contact at the epitaxy layer and substrate.

Growing community of inventors

Westford, MA, United States of America

Joel Lee Goodrich