France Telecom

Orange

Joël Lattmann

Christian Duret

Servane Bonjour

Sylvain Gombault

Mickael Meulle

Maryline Laurent Maknavicius

Valéry Laspreses

Herve Guesdon

Hervé Guesdon

Mihaela Oprescu

Francis Rischette

Olivier Paul

A control method is provided for controlling a load state of a physical link between two physical network nodes in a physical network. A physical link carries a plurality of virtual links, and a virtual link connects together two virtual nodes belonging to a virtual network. First and second metrics are associated with the virtual link. The control method includes the following steps implemented by one of the two physical network nodes: a step of detecting a load state of a physical link; a step of identifying a virtual link for which a present metric is the first metric; and a step of sending a command to the virtual node carried by the physical node and to which the identified virtual link is connected, the command requesting a modification of the present metric from the first metric to the second metric for the virtual link.

Technique for controlling a load state of a physical link carrying a plurality of virtual links

The invention relates to a tri-type memory device comprising a compression mechanism. According to the invention, the memory stores binary patterns that are associated with respective references. Data chains are analyzed by successive section of K bits (K&#x3e;1) in order to extract one of the references when there is a match with a stored binary pattern associated with said reference. The memory is organized into several successive memory cell states, the analysis of the (i+1)-th section of a chain providing access to a cell of stage i&#x2267;0. Each non-empty cell of a stage i&#x2267;0 contains one of the following: a register-type analysis tracking pointer designating a register of 2cells of stage i+1; a linear-type analysis tracking pointer designating a zone of one or two cells forming a reduced register of stage i+1; or a reference associated with a stored binary pattern.

Trie-type memory device with a compression mechanism

A Trie-type associative memory is used for an analysis of binary strings situated at defined locations of data packets. An analysis tree is established, which comprises stages associated with the locations, and paths each arriving at an action attributed on the basis of the values of the binary strings read from a data packet. The tree is then transcribed into the Trie memory.

Method for configuring a trie memory for the processing of data packets, and packet-processing device implementing such a method

Different portions of a header of each packet containing protocol data are analyzed in succession from different gate registers of the TRIE memory. As a packet arrives, its header is stored in a buffer memory and a first portion of the stored header is analyzed. Each analysis of a portion of header produces either the forwarding reference associated with the packet or an intermediate reference containing a first code, making it possible to locate at an arbitrary location of the buffer memory a next portion to be analyzed, and a second code, making it possible to locate at an arbitrary location of the TRIE memory a gate register from which this next portion is to be analyzed. Having analyzed the first portion of a stored header, the subsequent portions thereof are analyzed in accordance with the first and second codes contained in the intermediate references produced in succession until the forwarding reference is produced.

Method of associating forwarding references with data packets by means of a TRIE memory, and packet processing device applying such method

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Champs sur Marne, France

Joël Lattmann