Texas Instruments Corporation

Joel J Graber

Lee Doyle Whetsel

Sanjive Agarwala

Donald Edward Steiss

Bryan David Sheffield

Duy-Loan T Le

Manjeri Krishnan

Timothy David Anderson

Raguram Damodaran

Jonathan H Shiell

John M Johnsen

James O Bondi

Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure improves upon low power Scan and Scan-BIST methods. The improvement allows the low power Scan and Scan-BIST architectures to achieve a delay test capability equally as effective as the delay test capabilities used in conventional scan and Scan-BIST architectures.

Delay testing capturing second response to first response as stimulus

Scan path delay testing with two memories and three subdivisions

Memory coupling scan input to first of scan path segments

Capturing response after simultaneously inputting last stimulus bit in scan path subdivisions

Segmented scan paths with cache bit memory inputs

This invention operates to select a drive code for an adjustable drive strength transistor in a drive buffer. The drive code is determined employing a scaled-down drive transistor employing varying drive codes compared with a standard. The thus determined drive code is combined with an offset to generate the drive code for the adjustable strength transistor.

Adjusting output buffer timing based on drive strength

Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present invention improves upon low power Scan and Scan-BIST methods. The improvement allows the low power Scan and Scan-BIST architectures to achieve a delay test capability equally as effective as the delay test capabilities used in conventional scan and Scan-BIST architectures.

Response bits as stimulus in subdivided scan path delay test

The pBIST solution to memory testing is a balanced hardware-software oriented solution. pBIST hardware provides access to all memories and other such logic (e.g. register files) in pipelined logic allowing back-to-back accesses. The approach then gives the user access to this logic through CPU-like logic in which the programmer can code any algorithm to target any memory testing technique required. Because hardware inside the chip is used at-speed, the full device speed capabilities are available. CPU-like hardware can be programmed and algorithms can be developed and executed after tape-out and while testing on devices in chip form is in process.

Programmable built in self test of memory

Electrical fuses (eFuses) are applied to the task of memory performance adjustment to improve upon earlier fuse techniques by not requiring an additional processing step and expensive equipment. Standard electrical fuse (eFuse) hardware chains provide a soft test feature wherein the effect of memory slow-down can be tested prior to actually programming the fuses. Electrical fuses thus provide a very efficient non-volatile method to match the logic-memory interface through memory trimming, drastically cutting costs and cycle times involved.

Electrical fuse control of memory slowdown

Low power delay test capabilities in Scan and Scan-BIST architectures occur by inserting a first cache bit memory between the scan input lead and the serial input to a first scan path segment. When the first segment is serially loaded, the last test bit remains in the first cache bit memory. When a last scan path segment is serially loaded and when the last bit is loaded into the last scan path segment, the last bit in the first cache bit memory is simultaneously loaded into the first scan path segment. This presents the desired stimulus signals to the logic circuits. The next clock signal to the scan path segments then captures the response from the logic circuits.

IC with cache bit memory in series with scan segment

In a method embodiment (10), the method operates a microprocessor (110), and the microprocessor has an instruction set. The method first (11) stores an identifier code uniquely identifying the particular microprocessor in a one-time programmable register. The method second (12) issues to the microprocessor an identifier request instruction from the instruction set. The method then, and in response to the identifier request instruction, provides (18) from the microprocessor an identifier code. Other circuits, systems, and methods are also disclosed and claimed.

Circuits, systems, and methods for uniquely identifying a microprocessor

A microprocessor (10) operating in response to a clock signal (CLK) having a clock period. The microprocessor includes a readable memory (16), and this readable memory stores code (BIST) for performing diagnostic evaluations of the microprocessor. The diagnostic evaluations include a first evaluation to occur under non-failure operation at a first clock period (24) and a last evaluation to occur under non-failure operation at a last clock period (26). The microprocessor further includes circuitry (14) for issuing a series of addresses to the readable memory in order to address the code for performing diagnostic evaluations of the microprocessor. Still further, the microprocessor includes a conductor (D0) externally accessible and for providing a signal from the microprocessor. Lastly, the microprocessor includes circuitry (12) for outputting a diagnostic signal on the externally accessible conductor during performance of the diagnostic evaluations. Given the externally accessible conductor, divergence of the diagnostic signal from a predetermined pattern before the last dock period indicates a failure of the diagnostic evaluations before the last clock period.

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Richardson, TX, United States of America

Joel J Graber