Commissariat a L'energie Atomique

Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Joel Hartmann

Pierre Jeuch

Francois Buiguez

Device having an electrically erasable, non-volatile memory and its production process. In a storage area the device has at least one memory cell (12) of the floating grid type with a source (16) and a drain (18) separated by a channel region (14). According to the invention, the device also comprises means (44,38) for applying a memory cell erasing voltage to the channel region (14), independently of the memory cells of adjacent areas, as a result of a complete electrical isolation or insulation of each area. Application to the production of non-volatile memories which can be carried in satellites for replacing EPROM memories.

Device having an electrically erasable non-volatile memory and process

Triple gate flash-type EEPROM memory and its production process

An improved integrated circuit and fabrication method for forming the improved integrated circuit is described. The method includes an anisotropic etching, without the use of either masks or photolithography, which removes insulating material from contact openings, but keeps insulating material on the sides of conductive layers, preventing inadvertent short circuits from the contact openings to the conductive layers. The maskless etching method makes it possible to avoid mask-wafer alignment errors and therefore frees designers to perfectly center contact openings within insulative regions without taking into account the surface area tolerances required under prior art fabrication methods. This freedom allows designers to design more highly integrated devices. The particular embodiments of the semiconductor integrated circuit may include floating gates (47) and control gates (52) covered with an upper oxide layer (53) on which electrical connection lines (11) have been installed.

Method for fabricating semiconductor memory device

Method for producing a non-volatile memory cell and obtained memory cell. This method consists of embodying strips in a stacking of one nonconducting film and one conductive film, both films intended to respectively form the gate nonconductors (210) and the floating gates (208) of transistors, of forming spacers (230) on the flanks of the strips of said stacking, of eliminating the spacers on the side of the drains of the memory points to be embodied, of implanting ions of a type with conductivity differing from that of the substrate by using the remaining spacers and the strips of said stacking as a mask so as to form the sources and drains (214, 216) of the transistors, respectively offset and aligned with respect to said strips, of eliminating the remaining spacers, of forming a thin electric nonconducting film (208) on the sources and drains of the transistors, of embodying conductive strips (206a) perpendicular to the diffused source and drain zones, and of etching the strips of said stacking by using the conductive strips as a mask.

Method for producing a non-volatile memory cell using spacers

A method of making an electric contact of an MIS integrated circuit includes the following stages: depositing a thick film made of one first electric nonconductor on the integrated circuit provided with this element; depositing on the first nonconductor film a crash or barrier film made of a highly resistive material or a nonconductor able to be etched selectively with respect to the first nonconductor and a second electric nonconductor; forming opposite the active element a first opening in the barrier film and fixing the dimensions at the level of the active element of the electric contact to be embodied; depositing on the resulting structure obtained at least one second nonconducting film forming a second opening in the second nonconducting film, the second opening having a width larger than that the first opening; etching of the first nonconductor exposed during the previous step by using the etched barrier film as a mask, thus forming an electric contact hole of the active element, and metallizing of this contact hole.

Method for embodying an electric circuit on an active element of an MIS

A method for interconnecting the active zones and/or gates of CMOS integrated circuits. The method comprises, during the formation of the gates in a first conductive coating, defining in the latter the dimensions of the connections to be produced, and wherein following the formation of the active zones, the gates are laterally insulated and then a second conductive coating producing the desired connections is deposited on the complete circuit, with the exception of the lateral insulation.

Method for interconnecting the active zones and gates of CMOS integrated

A device for checking the mobile electrical charges in a MOS integrated circuit having a wafer support, a polarization means applying a potential difference between the two faces of the silicon wafer on which are formed the integrated circuits by means of two electrodes, one constituted by a conductive diaphragm covering the silicon wafer and which is kept in contact with the silicon wafer by a pressure difference between these two faces, while the other is constituted by the electrically conductive wafer support.

Device for checking mobile electrical charges in a MOS integrated circuit

Process for the autopositioning of a local field oxide relative to an insulating trench. This process consists of forming at least one first insulating coating on a silicon substrate, producing a second insulating coating on the first coating, anisotropically etching the first and second coating until the region of the substrate in which the trench is to be formed is exposed, forming insulating spacers on the etched flanks of the first and second coatings, anisotropically etching the substrate region in order to form the trench, the second etched coating and the spacers used as a mask for said etching, eliminating the mask, forming the insulating edges in the trench, filling said trench with a material and forming the field oxide.

Process for the autopositioning of a local field oxide with respect to

A method for interconnecting the active zones and/or the gates of a C/MOS integrated circuit characterized in that, after producing the constituent elements of the integrated circuit with the exception of the connections, on the complete circuit is directly deposited a coating of a conductive material, which is then etched in order to form the desired connection.

Method for interconnecting the active zones and/or the gates of a C/MOS

This process consists of depositing a first conductive coating on the complete circuit, depositing on said coating a filling material used for filling the contact hole, the surface of said material being substantially planar, carrying out an anisotropic etching of said filling material so as to expose those parts of the first conductive coating located outside the contact hole and only retaining that part of said filling material which fills the contact hole, depositing on the structure obtained a second conductive coating in which the interconnection line will be formed, producing in the second conductive coating a resin mask used for defining the dimensions of the line, eliminating those parts of the second and first conductive coatings which are free from the mask and eliminating the mask.

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Claix, France

Joel Hartmann