Ciena Corporation

Aruba Networks, Inc.

Joel Fredric Adam

Darren Engelkemier

Daniel E Klausmeier

Edward Everett Sprague

Keerti G Melkote

Jerry Martinson

Pankaj S Manglik

In one embodiment, the invention relates to a serial line circuit that comprises a serial information (SI) bus and at most two isolators interposed between a pair of programmable devices. In the TRANSMIT direction, a first programmable device is configured to multiplex serial data received from a plurality of serial UARTs and to route such data to the second programmable device over the SI bus and through a first isolator. In the RECEIVE direction, the second programmable device is configured to sample data from a plurality of serial interconnects and to route the sampled data to the first programmable device. The sampled data is routed over the SI bus and through a second isolator. The data transmission over the SI bus is in accordance with a proprietary serial transmission protocol described below.

Serial line circuit, an apparatus implemented with a serial line circuit, and method thereof

In general, one embodiment of the invention is a radio access point (RAP) system adapted to a wired network. The RAP system comprises a radio access point and a switch coupled together by an interconnect. The radio access point includes components to digitally sample a detected, wireless analog signal thereby producing digital data. The digital data is placed into a frame for transmission over the interconnect. The switch includes a radio access point (RAP) component that recovers the digital data from the frame transmitted over the interconnect. The RAP component processes the digital data to recover media access control (MAC) frames containing data for subsequent transmission over the wired network.

Modular radio access point

A switch is provided that receives user information through a plurality of framer circuits, which group the user information into frames. The frames are fed to a switch fabric including an array of switch elements, each having a switch matrix for routing each frame to a desired output in accordance with configuration data stored in a first table coupled to the switch matrix. If different outputs are desired, i.e., the switch matrix is to be reconfigured, a switch control circuit supplies additional switch configuration data to the frames through the inputs along with additional user information to be routed through the switch. While the additional switch configuration data is stored in a second table, data flow remains uninterrupted through the switch matrix. Once storage of the additional configuration data into the second table is complete, however, the switch control circuit inserts a table select signal into the frames, to thereby couple the second table to the switch so that the switch matrix is configured in accordance with the additional switch configuration data. Subsequent frames are then routed through the reconfigured switch matrix. The first and second tables can thus be alternately updated and coupled to the switch matrix to appropriately reconfigure the switch without affecting existing connections established through the switch. 'Hitless switchover' is therefore achieved.

Switch fabric architecture and techniques for implementing rapid hitless switchover

Consistent with the present invention, programmable input and output buffers are provided on each port of each stage of a distributed system in order to reduce data skew and preserve data synchronization. The programmable buffers provide the ability to add delay to data paths having less skew to compensate or match the skew associated with data paths having greater skew. Accordingly, the programmable buffers can equalize data skew and preserve data synchronization at each stage in the distributed system. As a result, individual stages can be placed farther apart, thereby facilitating larger distributed systems.

Techniques and architectures for implementing a data skew equalizer for data alignment in a distributed system

A switch is provided that receives user information through a plurality of framer circuits, which group the user information into frames. The frames are fed to a switch fabric including an array of switch elements, each having a switch matrix for routing each frame to a desired output in accordance with configuration data stored in a first table coupled to the switch matrix. If different outputs are desired, i.e., the switch matrix is to be reconfigured, a switch control circuit supplies additional switch configuration data to the frames through the inputs along with additional user information to be routed through the switch. While the additional switch configuration data is stored in a second table, data flow remains uninterrupted through the switch matrix. Once storage of the additional configuration data into the second table is complete, however, the switch control circuit inserts a table select signal into the frames, to thereby couple the second table to the switch so that the switch matrix is configured in accordance with the additional switch configuration data. Subsequent frames are then routed through the reconfigured switch matrix. The first and second tables can thus be alternately updated and coupled to the switch matrix to appropriately reconfigure the switch without affecting existing connections established through the switch. &ldquo;Hitless switchover&rdquo; is therefore achieved.

An exemplary embodiment of the invention is a method for encoding data into a 48B/50B format for transmission over a serial link. A data stream that includes characters is received and segmented into a six-character block. The block of six characters is translated into a 50-bit byte frame in 48B/50B format. A 48-bit word is created from the block of six characters by encoding the characters contained in the block. The 48-bit word is scrambled and a 2-bit synchronization sequence is appended to the scrambled 48-bit word. The result is the 50-bit byte frame in 48B/50B format. An alternate embodiment of the present invention includes a method for decoding data from the 48B/50B format.

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Cupertino, CA, United States of America

Joel Fredric Adam