Google Inc.

Joel Dylan Coburn

Albert Borchers

Robert S Sprinkle

Christopher Lyle Johnson

Benjamin Charles Serebrin

Monish Shah

Methods, systems, and apparatus for determining whether an access bit is set for each page table entry of a page table based on a scan of the page table with at least one page table walker, the access bit indicating whether a page associated with the page table entry was accessed in a last scan period; incrementing a count for each page in response to determining that the access bit is set for the page table entry associated with the page; resetting the access bit after determining whether the access bit is set for each page table entry; receiving a request to access, from a main memory, a first page of data; initiating a page fault based on determining that the first page of data is not stored in the main memory; and servicing the page fault with a DMA engine.

Hybrid memory management

Methods, systems, and apparatus for receiving a request to access, from a main memory, data contained in a first portion of a first page of data, the first page of data having a first page size; initiating a page fault based on determining that the first page of data is not stored in the main memory; allocating a portion of the main memory equivalent to the first page size; transferring the first portion of the first page of data from the secondary memory to the allocated portion of the main memory without transferring the entire first page of data; and updating a first page table entry associated with the first portion of the first page of data to point to a location of the allocated portion of the main memory to which the first portion of the first page of data is transferred.

Memory management supporting huge pages

A method includes deploying non-volatile random access memory (NVRAM) coupled to a processor or central processing unit (CPU) core of a computing device as a peripheral device via an input/output (I/O) bus, and providing a NVRAM application programming interface (API) for the CPU core to conduct NVRAM read and write operations. Providing the NVRAM API includes allocating a single memory buffer per command to hold data transferred to or from the NVRAM. The method includes configuring the processor in conjunction with the NVRAM API to set up command queues inside in the host Memory Mapped Input Output (MMIO) space.

Non-volatile memory device application programming interface

Methods, systems, and apparatus for receiving a request to access, from a main memory, a first cache line of a page of data; determining that the first cache line is not stored in the main memory and is stored in a secondary memory, and in response: transferring the first cache line of the page of data from the secondary memory to the main memory without transferring the entire page of data, wherein a remaining portion of the page of data remains stored in the secondary memory; updating a page table entry associated with the page of data to point to a location of the page of data in the main memory; and transferring the remaining portion of the page of data from the secondary memory to the main memory.

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Mountain View, CA, United States of America

Joel Dylan Coburn