Infineon Technologies Ag

Intel Mobile Communications Gmbh

Morphics Technology, Inc.

Intel Deutschland Gmbh

Joel D Medlock

David Morris Holmes

Uma Jha

Keith Rieken

Christopher Woodthorpe

Ravi Subramanian

Song Chen

Andrea Y J Chen

Madasamy Kartheepan

Kenneth M Hesky

Raju R Joag

Louay A Jalloul

Michael Kohlmann

Paul Chou

Murali Krishnan

David M Holmes

A dynamically reconfigurable universal transmitter system is disclosed herein. The electronic device includes multiple transmitter resources for generating transmission signals, an output bus; and an antenna summer coupled to the output bus. The output bus is selectively coupled to the plurality of transmitter resources and it selectively receives transmission signals from the plurality of transmission resources. The antenna summer stores transmission signals received on the output bus.

Dynamically reconfigurable universal transmitter system

The present invention provides a virtual machine interface (VMI) and an application programming interface (API) usable in conjunction with a reconfigurable wireless network communication apparatus. The reconfigurable wireless network communication apparatus comprises a plurality of hardware kernels. The apparatus can be reconfigured to support different or modified communication protocols over time. The VMI comprises a library of software objects. By configuring VMI software objects, a programmer selects the communication protocol used by the reconfigurable wireless network communication apparatus. The API of the present invention provides higher level management of the communication protocol used by a reconfigurable wireless network communication apparatus. The API comprises a library of high level software objects that further abstract hardware details of the apparatus.

Virtual machine interface for hardware reconfigurable and software programmable processors

A dynamically reconfigurable universal transmitter system is disclosed herein. The electronic device includes multiple transmitter resources for generating transmission signals, an output bus, and an antenna summer coupled to the output bus. The output bus is selectively coupled to the plurality of transmitter resources and it selectively receives transmission signals from the plurality of transmission resources. The antenna summer stores transmission signals received on the output bus.

A method for designing a time-sliced and multi-threaded architecture comprises the steps of conducting a thorough analysis of a range of applications and building a specific processor to accommodate the range of applications. In one embodiment, the thorough analysis includes extracting real time aspects from each application, determining optimal granularity in the architecture based on the real time aspects of each application, and adjusting the optimal granularity based on acceptable context switching overhead.

Method and apparatus for time-sliced and multi-threaded data processing in a communication system

A virtual machine interface for a separate reconfigurable wireless network communication apparatus comprising a plurality of software objects, wherein each software object is associated with a hardware kernel assigned to the reconfigurable wireless network communication apparatus, each software object configured such that a change in the software object results in a change in the hardware kernel associated with the software object. The virtual machine interface has information as to types and numbers of software objects and values associated with the software objects necessary to implement a selected wireless communication protocol.

A method for processing data in a spread spectrum system, including decimating a data rate of received spread spectrum data by a decimation factor to a decimated rate; storing the received spread spectrum data into a memory at the decimated rate; interpolating the decimated rate by an interpolation factor to an interpolated rate; and reading the received spread spectrum data from the memory at the interpolated rate.

Method for processing data in a spread spectrum system

An apparatus and method for calculating and implementing a Fibonacci mask for a code generator is disclosed herein. The first step receives a desired code offset from a reference code state in a Fibonacci field. Next, a field vector in a Galois field with the same code offset sought in the first field is calculated. In the next step, the first field vector is transformed into a second field vector, which is operable as a mask in the Galois LFSR. The transform step is accomplished by multiplying the Galois field vector by a linear N&#xd7;N transformation matrix to obtain the Fibonacci field vector. And the N&#xd7;N transformation matrix is obtained from iterated states of the Fibonacci LFSR.

Apparatus and method for calculating and implementing a Fibonacci mask for a code generator

An embodiment of the present invention described in the specification and the drawings is an apparatus and method for code correlation in spread spectrum communication systems. The apparatus receives a data sequence, and offsets the data sequence with a fixed sub-chip delay. The data sequence and the offset data sequence are each despread with a locally generated code sequence. The despread results are summed and accumulated. The accumulated results may then be used to achieve a lower 'miss' probability during code correlation.

Apparatus and method for sub-chip offset correlation in spread-spectrum communication systems

A wireless spread spectrum communication platform for processing a communication signal is disclosed herein. The wireless communication platform includes a first computing element, a second computing element, and a reconfigurable interconnect. The first computing element is coupled to the second computing element via the reconfigurable interconnect. A design configuration of the first computing element is heterogeneous with respect to a design configuration of the second computing element. The reconfigurable interconnect has an uncommitted architecture, thereby allowing it to be configured by an outside source to couple portions of the first reconfigurable interconnect with portions of the second reconfigurable interconnect in a variety of combinations. The first computing element, the second computing element, and the reconfigurable interconnect operable to perform discrete functions suitable for processing of the communication signal.

Wireless spread spectrum communication platform using dynamically reconfigurable logic

Calculating of signal-to-interference ratio (SIR) of a mobile device in a wireless communication system. A communication signal transmitted by the mobile device is non-coherently processed. Interference power of the communication signal is estimated and then scaled, and the scaled estimated interference power is subtracted from the processed communication signal to thereby estimate signal power. The SIR is calculated by dividing the estimated signal power by the estimated interference power.

Signal-to-interference ratio estimation for CDMA

A Fast Hadamard Transform generator serially performs a Fast Hadamard Transform of a sampled signal from a first channel. The Fast Hadamard Transform generator comprises a series of stages. Each stage includes a shift register for serially receiving samples of the signal. Each stage further includes a two's complement generator for producing a two's complement of a first sample of the signal and a first multiplexer for selecting between a first sample of the signal and the two's complement of the first sample. A first adder then generates a sum of a second sample of the signal and the first sample and a difference of the second sample and the first sample and supplies the sum and the difference to the shift register of the next stage. In one embodiment the shift registers are implemented in random access memory.

Apparatus and method for Fast Hadamard Transforms

An apparatus for reducing storage requirements and for allowing reuse of multiple rake fingers in a spread spectrum system includes a decimation circuit having an associated decimation factor, a memory coupled to the decimation circuit, and an interpolation circuit having an interpolation factor coupled to the memory. The decimation circuit decimates the sampling rate of received data to produce a decimated rate. The received data is stored in the memory at the decimated rate. The decimated rate is later increased by the interpolation circuit by the interpolation factor when the stored data is retrieved from the memory. The memory is a circular buffer or a single port RAM that is accessible by multiple rake fingers substantially simultaneously via selector circuits.

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Los Gatos, CA, United States of America

Joel D Medlock